IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automatic generation of functional vectors using the extended finite state machine model
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A study in coverage-driven test generation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Automatic test pattern generation for functional RTL circuits using assignment decision diagrams
Proceedings of the 37th Annual Design Automation Conference
Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques
Proceedings of the 37th Annual Design Automation Conference
The GNU Prolog system and its implementation
SAC '00 Proceedings of the 2000 ACM symposium on Applied computing - Volume 2
Test Synthesis with Alternative Graphs
IEEE Design & Test
Coverage Metrics for Functional Validation of Hardware Designs
IEEE Design & Test
Functional Test Generation using Constraint Logic Programming
VLSI-SOC '01 Proceedings of the IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on/Chip: SOC Design Methodologies
An Application of Genetic Algorithms and BDDs to Functional Testing
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Coverage-directed validation of hardware models
Coverage-directed validation of hardware models
Functional vector generation for HDL models using linear programming and Boolean satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automatic constraint based test generation for behavioral HDL models
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We present a novel approach to generate functional vectors based on assertions for RTL design verification. Our approach combines program-slicing based design extraction, word-level SAT and dynamic searching techniques. Through design extraction, vectors generation need only concern about the design parts related to the given assertion, thus large practical designs can be handled. Constraints Logic Programming (CLP) naturally models mixed bit-level and word-level constraints, and word-level SAT techniques solve the mixed constraints in a unified framework, which gain perfect performance. Initial states derived from dynamic simulation can dramatically accelerate the searching process of functional vectors generation. A prototype system has been built, and the experimental results on some public benchmarks and industrial circuits demonstrate the efficiency of our approach and its applicability to large practical designs.