High-level transformations for minimizing syntactic variances
DAC '93 Proceedings of the 30th international Design Automation Conference
A BIST scheme for RTL controller-data paths based on symbolic testability analysis
DAC '98 Proceedings of the 35th annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Simulation vector generation from HDL descriptions for observability-enhanced statement coverage
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Testability analysis and insertion for RTL circuits based on pseudorandom BIST
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
High-coverage ATPG for datapath circuits with unimplemented blocks
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Sequential Circuit Test Generation Using Dynamic State Traversal
EDTC '97 Proceedings of the 1997 European conference on Design and Test
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Assertion-based automated functional vectors generation using constraint logic programming
Proceedings of the 14th ACM Great Lakes symposium on VLSI
EURASIP Journal on Applied Signal Processing
Mixed hierarchical-functional fault models for targeting sequential cores
Journal of Systems Architecture: the EUROMICRO Journal
RTL DFT Techniques to Enhance Defect Coverage for Functional Test Sequences
Journal of Electronic Testing: Theory and Applications
Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints
Journal of Electronic Testing: Theory and Applications
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In this paper, we present an algorithm for generating test patterns automatically from functional register transfer level (RTL) circuits that target detection of stuck-at faults in the circuit at the logic level. To do this we utilize a data structure named assignment decision diagram which has been proposed previously in the field of high level synthesis. The advent of RTL synthesis tools have made functional RTL designs widely popular. This paper addresses the problem of test pattern generation directly at this level due to a number of advantages inherent at the RTL. Since the number of primitive elements at the RTL is usually lesser than the logic level, the problem size is reduced leading to a reduction in the test generation time over logic-level ATPG. A reduction in the number of backtracks can lead to improved fault coverage and reduced test application time over logic-level techniques. The test patterns thus generated can also be used to perform RTL-RTL and RTL-logic validation. The algorithm is very versatile and can tackle almost any type of single-clock design though performance varies according to the design style. It gracefully degrades to an inefficient logic-level ATPG algorithm if it is applied to a logic-level circuit. Experimental results demonstrate that over 1000 times reduction in test generation time can be achieved by this algorithm on certain types of RTL circuits without any compromise in fault coverage.