Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Bridge: a versatile behavioral synthesis system
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Condition graphs for high-quality behavioral synthesis
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A transformation-based approach for storage optimization
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Equivalence checking of datapaths based on canonical arithmetic expressions
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
From VHDL to efficient and first-time-right designs: a formal approach
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Recent developments in high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The maximal VHDL subset with a cycle-level abstraction
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Automatic test pattern generation for functional RTL circuits using assignment decision diagrams
Proceedings of the 37th Annual Design Automation Conference
Execution condition analysis in high level synthesis: a unified approach
ISSS '00 Proceedings of the 13th international symposium on System synthesis
On the fundamental limitations of transformational design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A global approach to improve conditional hardware reuse in high-level synthesis
Journal of Systems Architecture: the EUROMICRO Journal
Introduction to High-Level Synthesis
IEEE Design & Test
SLIF: a specification-level intermediate format for system design
EDTC '95 Proceedings of the 1995 European conference on Design and Test
A BDD-based frontend for retargetable compilers
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Equivalence checking of arithmetic expressions using fast evaluation
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
Dynamic range estimation for nonlinear systems
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
An efficient evaluation and vector generation method for observability-enhanced statement coverage
Journal of Computer Science and Technology
Data-flow transformations using Taylor expansion diagrams
Proceedings of the conference on Design, automation and test in Europe
EURASIP Journal on Applied Signal Processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Mixed hierarchical-functional fault models for targeting sequential cores
Journal of Systems Architecture: the EUROMICRO Journal
Automatic constraint based test generation for behavioral HDL models
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimization of data-flow computations using canonical TED representation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
PSL Assertion Checking Using Temporally Extended High-Level Decision Diagrams
Journal of Electronic Testing: Theory and Applications
Expression equivalence checking using interval analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints
Journal of Electronic Testing: Theory and Applications
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