CHOP: A constraint-driven system-level partitioner
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Specification partitioning for system design
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
High-level transformations for minimizing syntactic variances
DAC '93 Proceedings of the 30th international Design Automation Conference
Specification and design of embedded systems
Specification and design of embedded systems
Experience with image compression chip design using unified system construction tools
DAC '94 Proceedings of the 31st annual Design Automation Conference
A method for partitioning UNITY language in hardware and software
EURO-DAC '94 Proceedings of the conference on European design automation
A Model and Methodology for Hardware-Software Codesign
IEEE Design & Test
Hardware-Software Cosynthesis for Digital Systems
IEEE Design & Test
Hardware-Software Cosynthesis for Microcontrollers
IEEE Design & Test
Information model of a compound graph representation for system and architecture level design
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Closeness metrics for system-level functional partitioning
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
I/O and performance tradeoffs with the FunctionBus during multi-FPGA partitioning
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Port calling: a transformation for reducing I/O during multi-package functional partitioning
ISSS '97 Proceedings of the 10th international symposium on System synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Procedure cloning: a transformation for improved system-level functional partitioning
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Co-synthesis and co-simulation of control-dominated embedded systems
Readings in hardware/software co-design
Automated design synthesis and partitioning for adaptive reconfigurable hardware
Hardware implementation of intelligent systems
On the hardware-software partitioning problem: System modeling and partitioning techniques
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Procedure cloning: a transformation for improved system-level functional partitioning
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Towards a Model for Hardware and Software Functional Partitioning
CODES '96 Proceedings of the 4th International Workshop on Hardware/Software Co-Design
Modifying Min-Cut for Hardware and Software Functional Partitioning
CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
Towards an integrated, model-based codesign environment
ECBS'99 Proceedings of the 1999 IEEE conference on Engineering of computer-based systems
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As methodologies and tools for chip-level design mature, design effort becomes focused on higher abstraction levels. Presently, much effort is focused on system-level design, where the key tasks include system component allocation, functional partitioning and transformation, and coarse estimation. However, commonly-used internal formats of functionality, such as the control-dataflow graph, are too fine-grained for the system level. We introduce a more abstract format, and we demonstrate its order-of-magnitude more efficient support of system design tasks and its support of practical designer interaction. The format is used by the SpecSyn system design environment, and can be extended to handle many new system design problems.