Verification of hardware descriptions by retargetable code generation
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Global scheduling independent of control dependencies based on condition vectors
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Representing conditional branches for high-level synthesis applications
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Computer system architecture (3rd ed.)
Computer system architecture (3rd ed.)
High-level transformations for minimizing syntactic variances
DAC '93 Proceedings of the 30th international Design Automation Conference
Instruction set extraction from programmable structures
EURO-DAC '94 Proceedings of the conference on European design automation
Tree-based mapping of algorithms to predefined structures
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Time-constrained code compaction for DSPs
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Concurrent analysis techniques for data path timing optimization
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Instruction selection for embedded DSPs with complex instructions
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
HDL-based modeling of embedded processor behavior for retargetable compilation
Proceedings of the 11th international symposium on System synthesis
Embedded software in real-time signal processing systems: design technologies
Readings in hardware/software co-design
Retargetable Generation of Code Selectors from HDL Processor Models
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Instruction-Set Modeling for ASIP Code Generation
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Effective compiler generation by architecture description
Proceedings of the 2006 ACM SIGPLAN/SIGBED conference on Language, compilers, and tool support for embedded systems
Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting
Journal of VLSI Signal Processing Systems
Compiler generation from structural architecture descriptions
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
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We present a unified frontend for retargetable compilers that performs analysis of the target processor model. Our approach bridges the gap between structural and behavioral processor models for retargetable compilation. This is achieved by means of instruction set extraction. The extraction technique is based on a BDD data structure which significantly improves control signal analysis in the target processor compared to previous approaches.