Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting

Authors:
Jianjiang Ceng;Weihua Sheng;Manuel Hohenauer;Rainer Leupers;Gerd Ascheid;Heinrich Meyr;Gunnar Braun
Affiliations:
Institute for Integrated Signal Processing Systems, Aachen University of Technology (RWTH), Aachen, Germany;Institute for Integrated Signal Processing Systems, Aachen University of Technology (RWTH), Aachen, Germany;Institute for Integrated Signal Processing Systems, Aachen University of Technology (RWTH), Aachen, Germany;Institute for Integrated Signal Processing Systems, Aachen University of Technology (RWTH), Aachen, Germany;Institute for Integrated Signal Processing Systems, Aachen University of Technology (RWTH), Aachen, Germany;Institute for Integrated Signal Processing Systems, Aachen University of Technology (RWTH), Aachen, Germany;CoWare, Inc., Aachen, Germany
Venue:
Journal of VLSI Signal Processing Systems
Year:
2006

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Abstract

Today's Application Specific Instruction-set Processor (ASIP) design methodology often employs centralized Architecture Description Language (ADL) processor models, from which software tools, such as C compiler, assembler, linker, and instruction-set simulator, can be automatically generated. Among these tools, the C compiler is becoming more and more important. However, the generation of C compilers requires high-level architecture information rather than low-level details needed by simulator generation. This makes it particularly difficult to include different aspects of the target architectureinto one single model, and meanwhile keeping consistency.This paper presents a modeling style, which is able to capture high- and low-level architectural information at the same time and make it possible to drive both the C compiler and the simulator generation without sacrificing the modeling flexibility. The proposed approach has been successfully applied to model a number of contemporary, real-world processor architectures.