Code generation using tree matching and dynamic programming
ACM Transactions on Programming Languages and Systems (TOPLAS)
Engineering a simple, efficient code-generator generator
ACM Letters on Programming Languages and Systems (LOPLAS)
Industrial experience using rule-driven retargetable code generation for multimedia applications
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Code generation algorithms for digital signal processors
Code generation algorithms for digital signal processors
Instruction selection, resource allocation, and scheduling in the AVIV retargetable code generator
DAC '98 Proceedings of the 35th annual Design Automation Conference
EXPRESSION: a language for architecture exploration through compiler/simulator retargetability
DATE '99 Proceedings of the conference on Design, automation and test in Europe
A Retargetable C Compiler: Design and Implementation
A Retargetable C Compiler: Design and Implementation
Instruction Scheduler Generation for Retargetable Compilation
IEEE Design & Test
A Graph Based Processor Model for Retargetable Code Generation
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Retargetable Generation of Code Selectors from HDL Processor Models
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Exploring Memory Hierarchy with ArchC
SBAC-PAD '03 Proceedings of the 15th Symposium on Computer Architecture and High Performance Computing
A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models
Proceedings of the conference on Design, automation and test in Europe - Volume 2
A novel approach for flexible and consistent ADL-driven ASIP design
Proceedings of the 41st annual Design Automation Conference
Flexible and Formal Modeling of Microprocessors with Application to Retargetable Simulation
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Effective compiler generation by architecture description
Proceedings of the 2006 ACM SIGPLAN/SIGBED conference on Language, compilers, and tool support for embedded systems
Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting
Journal of VLSI Signal Processing Systems
Compiler generation from structural architecture descriptions
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
Processor Description Languages
Processor Description Languages
Precise simulation of interrupts using a rollback mechanism
Proceedings of th 12th International Workshop on Software and Compilers for Embedded Systems
An early real-time checker for retargetable compile-time analysis
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
Automatically generating instruction selectors using declarative machine descriptions
Proceedings of the 37th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Versatile system-level memory-aware platform description approach for embedded MPSoCs
Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems
Converting intermediate code to assembly code using declarative machine descriptions
CC'06 Proceedings of the 15th international conference on Compiler Construction
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Efficient architecture exploration and design of application specific instruction-set processors (ASIPs) requires retargetable software development tools, in particular C compilers that can be quickly adapted to new architectures. A widespread approach is to model the target architecture in a dedicated architecture description language (ADL) and to generate the tools automatically from the ADL specification. For C compiler generation, however, most existing systems are limited either by the manual retargeting effort or by redundancies in the ADL models that lead to potential inconsistencies. We present a new approach to retargetable compilation, based on the LISA 2.0 ADL with instruction semantics, that minimizes redundancies while simultaneously achieving a high degree of automation. The key of our approach is to generate the mapping rules needed in the compiler's code selector from the instruction semantics information. We describe the required analysis and generation techniques, and present experimental results for several embedded processors.