A Graph Based Processor Model for Retargetable Code Generation

Authors:
Johan van Praet;Dirk Lanneer;Gert Goossens;Werner Geurts;Hugo de Man
Affiliations:
IMEC, kapeldreef 75, 300l Leuven, Belgium;IMEC, kapeldreef 75, 300l Leuven, Belgium;IMEC, kapeldreef 75, 300l Leuven, Belgium;IMEC, kapeldreef 75, 300l Leuven, Belgium;IMEC, kapeldreef 75, 300l Leuven, Belgium
Venue:
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Year:
1996

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Abstract

Embedded processors in electronic systems typically are tuned to a few applications. Development of processor specific compilers is prohibitively expensive and as a result such compilers, if existing, yield code of an unacceptable quality. To improve this code quality, we developed a retargetable and optimising code generator. It uses a graph based processor model that captures the connectivity, the parallelism and all architectural peculiarities of an embedded processor. In this paper, the processor model is presented and we formally define the code generation task, including code selection, register allocation and scheduling, in terms of this model.