Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Verification of hardware descriptions by retargetable code generation
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
BURG: fast optimal instruction selection and tree parsing
ACM SIGPLAN Notices
Data routing: a paradigm for efficient data-path synthesis and code generation
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Graph based retargetable microcode compilation in the MIMOLA design system
MICRO 20 Proceedings of the 20th annual workshop on Microprogramming
Local Microcode Compaction Techniques
ACM Computing Surveys (CSUR)
Global Code Selection of Directed Acyclic Graphs
CC '94 Proceedings of the 5th International Conference on Compiler Construction
Open-ended system for high-level synthesis of flexible signal processors
EURO-DAC '90 Proceedings of the conference on European design automation
Generating instruction sets and microarchitectures from applications
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Design of heterogeneous ICs for mobile and personal communication systems
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A tool for processor instruction set design
EURO-DAC '94 Proceedings of the conference on European design automation
Conflict modelling and instruction scheduling in code generation for in-house DSP cores
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Retargetable self-test program generation using constraint logic programming
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Time-constrained code compaction for DSPs
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Industrial experience using rule-driven retargetable code generation for multimedia applications
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Mapping statechart models onto an FPGA-based ASIP architecture
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Bit-alignment for retargetable code generators
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Code generation for core processors
DAC '97 Proceedings of the 34th annual Design Automation Conference
Instruction set selection for ASIP design
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
An ASIP design methodology for embedded systems
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Application-specific memory management for embedded systems using software-controlled caches
Proceedings of the 37th Annual Design Automation Conference
Code size minimization and retargetable assembly for custom EPIC and VLIW instruction formats
ACM Transactions on Design Automation of Electronic Systems (TODAES)
PSCP: a scalable parallel ASIP architecture for reactive systems
Proceedings of the conference on Design, automation and test in Europe
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Static resource models of instruction sets
Proceedings of the 14th international symposium on Systems synthesis
Instruction generation and regularity extraction for reconfigurable processors
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Specification and Design of Embedded Hardware-Software Systems
IEEE Design & Test
Static resource models for code-size efficient embedded processors
ACM Transactions on Embedded Computing Systems (TECS)
Synthesis of custom processors based on extensible platforms
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Efficient instruction encoding for automatic instruction set design of configurable ASIPs
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Automatic application-specific instruction-set extensions under microarchitectural constraints
Proceedings of the 40th annual Design Automation Conference
A unified scheduling model for high-level synthesis and code generation
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Incorporating compiler feedback into the design of ASIPs
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Describing instruction set processors using nML
EDTC '95 Proceedings of the 1995 European conference on Design and Test
A Specification Invariant Technique for Regularity Improvement between Flow-Graph Clusters
EDTC '96 Proceedings of the 1996 European conference on Design and Test
A Graph Based Processor Model for Retargetable Code Generation
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Instruction-Set Modeling for ASIP Code Generation
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Power-efficient flexible processor architecture for embedded applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Automatic application-specific instruction-set extensions under microarchitectural constraints
International Journal of Parallel Programming - Special issue: Workshop on application specific processors (WASP)
Automated Custom Instruction Generation for Domain-Specific Processor Acceleration
IEEE Transactions on Computers
Exploiting pipelining to relax register-file port constraints of instruction-set extensions
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
Instruction set synthesis with efficient instruction encoding for configurable processors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The Instruction-Set Extension Problem: A Survey
ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
A scalable synthesis methodology for application-specific processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
BURS-based instruction set selection
PSI'06 Proceedings of the 6th international Andrei Ershov memorial conference on Perspectives of systems informatics
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
The Instruction-Set Extension Problem: A Survey
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
A fast instruction set evaluation method for ASIP designs
EUC'06 Proceedings of the 2006 international conference on Embedded and Ubiquitous Computing
Accelerating loops for coarse grained reconfigurable architectures using instruction extensions
Proceedings of the 2011 ACM Symposium on Research in Applied Computation
Microprocessors & Microsystems
The Journal of Supercomputing
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