Instruction set definition and instruction selection for ASIPs
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
EXPRESSION: a language for architecture exploration through compiler/simulator retargetability
DATE '99 Proceedings of the conference on Design, automation and test in Europe
An instruction-level functionally-based energy estimation model for 32-bits microprocessors
Proceedings of the 37th Annual Design Automation Conference
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Proceedings of the 27th annual international symposium on Computer architecture
Lx: a technology platform for customizable VLIW embedded processing
Proceedings of the 27th annual international symposium on Computer architecture
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Proceedings of the ninth international symposium on Hardware/software codesign
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ACM Transactions on Design Automation of Electronic Systems (TODAES)
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VOLTA '99 Proceedings of the IEEE Alessandro Volta Memorial Workshop on Low-Power Design
High-level power modeling, estimation, and optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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ASIPs are designed specifically for a particular application or a set of applications. Their instruction sets must be carefully tailored to provide high performance as well as to meet non-functional constraints such as silicon area and power consumption. Traditionally, evaluation of different candidate instruction sets is all carried out through simulation. However, the growing design complexity and time-to-market pressure have rendered simulation increasingly infeasible. In this paper, we present an instruction level modeling method that can rapidly evaluates several important aspects of a selected instruction set. Experimental results show that we can prune a large number of candidate instruction sets with the model, accelerate design space exploration and alleviate the pressure on simulation