Digital transmission theory
Lattice basis reduction: improved practical algorithms and solving subset sum problems
Mathematical Programming: Series A and B
Instruction set definition and instruction selection for ASIPs
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Introduction to Space-Time Wireless Communications
Introduction to Space-Time Wireless Communications
Performance: complexity comparison of receivers for a LTE MIMO-OFDM system
IEEE Transactions on Signal Processing
Systolic like soft-detection architecture for 4x4 64-QAM MIMO system
Proceedings of the Conference on Design, Automation and Test in Europe
A Novel VLSI Architecture of Fixed-Complexity Sphere Decoder
DSD '10 Proceedings of the 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools
Decoding the golden code: a VLSI design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Implementation of a High Throughput Soft MIMO Detector on GPU
Journal of Signal Processing Systems
A universal lattice code decoder for fading channels
IEEE Transactions on Information Theory
Closest point search in lattices
IEEE Transactions on Information Theory
On maximum-likelihood detection and the search for the closest lattice point
IEEE Transactions on Information Theory
Soft-output sphere decoding: algorithms and VLSI implementation
IEEE Journal on Selected Areas in Communications
An FPGA embedded microcontroller
Microprocessors & Microsystems
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In comparison to single antenna systems, a wireless multiple-input multiple-output (MIMO) system provides higher throughput at no additional cost of bandwidth, but the high complexity of the detection algorithms poses a major challenge to the hardware implementation. Maximum likelihood (ML) MIMO detection guarantees optimal performance but implies huge processing complexity, which makes acceptable this approach only when the number of transmitting antennas is low and the adopted modulation scheme has a small cardinality. Sphere decoding (SD) is an efficient method that significantly reduces the average processing complexity with no performance penalty. Most of known sphere decoders have been implemented as application specific integrated circuits (ASICs), but the need for high degree of flexibility in MIMO detection makes interesting also application specific instruction set processor (ASIP) implementations. A single programmable ASIP can hardly reach the same processing speed as a fully dedicated ASIC; thus, parallel architectures with multiple concurrent ASIPs must be conceived to guarantee sufficient data throughput. The objective of this paper is to present a new ASIP-based implementation for the detection of MIMO signals. The processor supports multiple lattice modulation schemes (up to 64-QAM) and up to four transmitting antennas and it is able to run both ML and close to ML algorithms. A parallel architecture has been also designed with multiple ASIPs, which concurrently execute the detection algorithm on received symbols, a central unit acting as task scheduler, and a buffer for the compensation of non constant throughput. A dedicated bus handles the communication among allocated units. Each ASIP occupies a silicon area of 0.093mm^2 and runs at 400MHz when implemented on a 90nm CMOS technology. Achievable throughput depends on the adopted MIMO system and on the number of allocated ASIPs: a detector with 10ASIPs programmed to run ML detection on a 4x4 MIMO system with 64-QAM modulation offers a throughput of 78Mbps at signal-to-noise ratio SNR=18dB.