WARP, a Unified Wireless Network Testbed for Education and Research
MSE '07 Proceedings of the 2007 IEEE International Conference on Microelectronic Systems Education
Relaxed K-best MIMO signal detector design and VLSI implementation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Application-specific instruction set processor implementation of list sphere detector
EURASIP Journal on Embedded Systems
System architecture and implementation of MIMO sphere decoders on FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High throughput VLSI architecture for soft-output mimo detection based on a greedy graph algorithm
Proceedings of the 19th ACM Great Lakes symposium on VLSI
How GPUs can outperform ASICs for fast LDPC decoding
Proceedings of the 23rd international conference on Supercomputing
Reconfigurable real-time MIMO detector on GPU
Asilomar'09 Proceedings of the 43rd Asilomar conference on Signals, systems and computers
Algorithm and implementation of the K-best sphere decoding for MIMO detection
IEEE Journal on Selected Areas in Communications
Microprocessors & Microsystems
Integration of GPU Computing in a Software Radio Environment
Journal of Signal Processing Systems
An efficient GPU implementation of fixed-complexity sphere decoders for MIMO wireless systems
Integrated Computer-Aided Engineering
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Multiple-input multiple-output (MIMO) significantly increases the throughput of a communication system by employing multiple antennas at the transmitter and the receiver. To extract maximum performance from a MIMO system, a computationally intensive search based detector is needed. To meet the challenge of MIMO detection, typical suboptimal MIMO detectors are ASIC or FPGA designs. We aim to show that a MIMO detector on Graphic processor unit (GPU), a low-cost parallel programmable co-processor, can achieve high throughput and can serve as an alternative to ASIC/FPGA designs. However, careful architecture aware software design is needed to leverage the performance offered by GPU. We propose a novel soft MIMO detection algorithm, multi-pass trellis traversal (MTT), and show that we can achieve ASIC/FPGA-like performance and handle different configurations in software on GPU. The proposed design can be used to accelerate wireless physical layer simulations and to offload MIMO detection processing in wireless testbed platforms.