FreePDK: An Open-Source Variation-Aware Design Kit
MSE '07 Proceedings of the 2007 IEEE International Conference on Microelectronic Systems Education
Relaxed K-best MIMO signal detector design and VLSI implementation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System architecture and implementation of MIMO sphere decoders on FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Algorithm and implementation of the K-best sphere decoding for MIMO detection
IEEE Journal on Selected Areas in Communications
Performance: complexity comparison of receivers for a LTE MIMO-OFDM system
IEEE Transactions on Signal Processing
Microprocessors & Microsystems
Parallel High Throughput Soft-Output Sphere Decoding Algorithm
Journal of Signal Processing Systems
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MIMO systems (with multiple transmit and receive antennas) are becoming increasingly popular, and many next-generation systems such as WiMAX, 3-GPP LTE and IEEE802.11n wireless LANs rely on the increased throughput of MIMO systems with up to four antennas at receiver and transmitter. High throughput implementation of the detection unit for MIMO systems is a significant challenge especially for higher order modulation schemes. To achieve superior Bit Error Rate(BER) or Frame Error Rate (FER) performance, the detector has to provide soft values to advanced Forward Error Correction (FEC) schemes like Turbo Codes. This paper presents a systolic soft detector architecture for high dimensional(eg. 4x4, 64-QAM) MIMO systems. A Single detector core achieves, throughput of 215Mbps and power consumption of 23.6mW, whiles using only 33.1K gate equivalent(for l2 norm). Impressive SNR gains of almost 2dB are observed with respect to the hard detection counterpart over a block fading channel(at an FER of 1%). Additionally, the architecture can be stacked to give linear increase in throughput with linear increase in hardware resources.