Manifestations of heterogeneity in hardware/software co-design
DAC '94 Proceedings of the 31st annual Design Automation Conference
The triptych FPGA architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A memory selection algorithm for high-performance pipelines
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Characterizing the Memory Behavior of Compiler-Parallelized Applications
IEEE Transactions on Parallel and Distributed Systems
Synthesis of application-specific memory designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Instruction set definition and instruction selection for ASIPs
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Allocation of multiport memories for hierarchical data stream
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
The case for a configure-and-execute paradigm
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Reconfigurable computing: what, why, and implications for design automation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Surviving the SOC revolution: a guide to platform-based design
Surviving the SOC revolution: a guide to platform-based design
Closing the gap between ASIC and custom: an ASIC perspective
Proceedings of the 37th Annual Design Automation Conference
Data cache sizing for embedded processor applications
Proceedings of the conference on Design, automation and test in Europe
Low-Power CMOS Design
AMBA: Enabling Reusable On-Chip Designs
IEEE Micro
Specifying and Compiling Applications for RaPiD
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Improving Cache Behavior of Dynamically Allocated Data Structures
PACT '98 Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques
Customisable EPIC Processor: Architecture and Tools
Proceedings of the conference on Design, automation and test in Europe - Volume 3
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In the design of embedded systems, a processor architecture is a tradeoff between energy consumption, area, speed, design time, and flexibility to cope with future design changes. New versions in a product generation may require small design changes in any part of the design. We propose a novel processor architecture concept, which provides the flexibility needed in practice at a reduced power and performance cost compared to a fully programmable processor. The crucial element is a novel protocol combining an efficient, customized component with a flexible processor into a hybrid architecture.