Power optimization for FPGA look-up tables
Proceedings of the 1997 international symposium on Physical design
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
A novel high throughput reconfigurable FPGA architecture
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Extended design reuse trade-offs in hardware-software architecture mapping
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Flexible hardware acceleration for multimedia oriented microprocessors
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Interconnect pipelining in a throughput-intensive FPGA architecture
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Rothko: A Three-Dimensional FPGA
IEEE Design & Test
Balancing Logic Utilization and Area Efficiency in FPGAs
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Layout-Specific Circuit Evaluation in 3-D Integrated Circuits
Analog Integrated Circuits and Signal Processing
Architectural Design of a Three Dimensional FPGA
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
PITIA: an FPGA for throughput-intensive applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Power-efficient flexible processor architecture for embedded applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
The chimaera reconfigurable functional unit
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A reconfigurable architecture for hybrid CMOS/Nanodevice circuits
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Sharing of SRAM tables among NPN-equivalent LUTs in SRAM-based FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The amorphous FPGA architecture
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Designing a 3-D FPGA: switch box architecture and thermal issues
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High-performance, cost-effective heterogeneous 3D FPGA architectures
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
High-performance, cost-effective heterogeneous 3D FPGA architectures
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Making wide-issue VLIW processors viable on FPGAs
ACM Transactions on Architecture and Code Optimization (TACO) - HIPEAC Papers
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Field-programmable gate arrays (FPGAs) are an important implementation medium for digital logic. Unfortunately, they currently suffer from poor silicon area utilization due to routing constraints. In this paper we present Triptych, an FPGA architecture designed to achieve improved logic density with competitive performance. This is done by allowing a per-mapping tradeoff between logic and routing resources, and with a routing scheme designed to match the structure of typical circuits. We show that, using manual placement, this architecture yields a logic density improvement of up to a factor of 3.5 over commercial FPGAs, with comparable performance. We also describe Montage, the first FPGA architecture to fully support asynchronous and synchronous interface circuits.