A high-performance microarchitecture with hardware-programmable functional units
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
Applied cryptography (2nd ed.): protocols, algorithms, and source code in C
Applied cryptography (2nd ed.): protocols, algorithms, and source code in C
Placement and routing tools for the Triptych FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The triptych FPGA architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
PRISC: programmable reduced instruction set computers
PRISC: programmable reduced instruction set computers
Multi-FPGA systems
A reconfigurable multi-function computing cache architecture
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
High-performance carry chains for FPGA's
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The effect of reconfigurable units in superscalar processors
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Area & Time Limitations of FPGA-based Virtual Hardware
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Using On-Chip Configurable Logic to Reduce Embedded System Software Energy
FCCM '02 Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A dynamic instruction set computer
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Configuration management techniques for reconfigurable computing
Configuration management techniques for reconfigurable computing
Novel architecture for loop acceleration: a case study
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Architecture and compilation for data bandwidth improvement in configurable embedded processors
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Performance improvements from partitioning applications to FPGA hardware in embedded SoCs
The Journal of Supercomputing
NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture
Proceedings of the 43rd annual Design Automation Conference
A synthesizable datapath-oriented embedded FPGA fabric
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Architecture and compiler optimizations for data bandwidth improvement in configurable processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Synthesizable Datapath-Oriented Embedded FPGA Fabric for Silicon Debug Applications
ACM Transactions on Reconfigurable Technology and Systems (TRETS) - Special edition on the 15th international symposium on FPGAs
A partitioning flow for accelerating applications in processor-FPGA systems
ICCOMP'05 Proceedings of the 9th WSEAS International Conference on Computers
Journal of Systems Architecture: the EUROMICRO Journal
Dynamic coprocessor management for FPGA-enhanced compute platforms
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
Design space exploration for field programmable compressor trees
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
Application Domain Specific Embedded FPGAs for Flexible ISA-Extension of ASIPs
Journal of Signal Processing Systems
Dynamically Adapted Low Power ASIPs
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
SORU: A Reconfigurable Vector Unit for Adaptable Embedded Systems
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
An Application Development Framework for ARISE Reconfigurable Processors
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
A hybrid nano/CMOS dynamically reconfigurable system—Part I: Architecture
ACM Journal on Emerging Technologies in Computing Systems (JETC)
ACM Journal on Emerging Technologies in Computing Systems (JETC)
An asymmetric distributed shared memory model for heterogeneous parallel systems
Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems
Compiling for reconfigurable computing: A survey
ACM Computing Surveys (CSUR)
On the implementation of virtual array using configuration plane
APPT'07 Proceedings of the 7th international conference on Advanced parallel processing technologies
Flexible and Efficient Instruction-Grained Run-Time Monitoring Using On-Chip Reconfigurable Fabric
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
The Instruction-Set Extension Problem: A Survey
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Thread Warping: Dynamic and Transparent Synthesis of Thread Accelerators
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Performance improvements of microprocessor platforms with a coarse-grained reconfigurable data-path
ICS'06 Proceedings of the 10th WSEAS international conference on Systems
The ARISE approach for extending embedded processors with arbitrary hardware accelerators
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient resource sharing architecture for multistandard communication system
VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions
Augmenting DR-ASIP flexibility through multi-mode custom instructions
ACM SIGARCH Computer Architecture News
Performance gains from partitioning embedded applications in Processor-FPGA socs
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Memory-based computing for performance and energy improvement in multicore architectures
Proceedings of the great lakes symposium on VLSI
BSArc: blacksmith streaming architecture for HPC accelerators
Proceedings of the 9th conference on Computing Frontiers
A just-in-time customizable processor
Proceedings of the International Conference on Computer-Aided Design
| Hi-index | 0.00 |
By strictly separating reconfigurable logic from the host processor, current custom computing systems suffer from a significant communication bottleneck. In this paper, we describe Chimaera, a system that overcomes the communication bottleneck by integrating reconfigurable logic into the host processor itself. With direct access to the host processor's register file, the system enables the creation of multi-operand instructions and a speculative execution model key to high-performance, general-purpose reconfigurable computing. Chimaera also supports multi-output functions and utilizes partial run-time reconfiguration to reduce reconfiguration time. Combined, the system can provide speedups of a factor of two or more for general-purpose computing, and speedups of 160 or more are possible for hand-mapped applications.