Hardware/software partitioning of software binaries
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
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Proceedings of the tenth international symposium on Hardware/software codesign
Dynamic hardware/software partitioning: a first approach
Proceedings of the 40th annual Design Automation Conference
The case for reconfigurable hardware in wearable computing
Personal and Ubiquitous Computing
ACM Transactions on Embedded Computing Systems (TECS)
The chimaera reconfigurable functional unit
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An EDF schedulability test for periodic tasks on reconfigurable hardware devices
Proceedings of the 2006 ACM SIGPLAN/SIGBED conference on Language, compilers, and tool support for embedded systems
Towards Novel Approaches in Design Automation for FPGA Power Optimization
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Demonstration of an in-band reconfiguration data distribution and network node reconfiguration
Proceedings of the Conference on Design, Automation and Test in Europe
Location, location, location: the role of spatial locality in asymptotic energy minimization
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
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We examine the energy savings possible by remapping critical software loops from a microprocessor to configurable logic appearing on the same-chip in commodity chips now commercially available. That logic is typically intended to implement peripherals and coprocessors without increasing chip count 驴 but we show that reduced software energy is an additional benefit, making such chips even more useful. We find critical software loops and re-implement them in the configurable logic such that a repeating software task completes sooner, allowing us to put the system in a low-power state for longer periods, thus reducing energy. We use simulations and estimations for a hypothetical device having a 32-bit MIPS processor plus configurable logic, yielding energy savings of 25%, increasing to 39%assuming voltage scaling. We physically measured several examples running on two commercial single-chip devices having an 8-bit 8051 microprocessor plus configurable logic and a 32-bit ARM microprocessor with configurable logic, with energy savings of 71% and 53% respectively, increasing to an estimated 89% and 75% assuming voltage scaling.