Dynamic power consumption in Virtex™-II FPGA family
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Using On-Chip Configurable Logic to Reduce Embedded System Software Energy
FCCM '02 Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Power Estimation and Power Measurement of Xilinx Virtex FPGAs: Trade-Offs and Limitations
SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
Methodology for high level estimation of FPGA power consumption
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Systematic Characterization of Programmable Packet Processing Pipelines
FCCM '06 Proceedings of the 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Proceedings of the conference on Design, automation and test in Europe
System-level power-performance tradeoffs for reconfigurable computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The exploitation of reconfigurable architectures is currently increasing for high-performance applications e.g. signal processing systems. Until now however, general purpose processors are typically applied for lowpower applications partly due to the un-optimized design process of FPGA systems. Currently, the increasing requirements even on low-power applications force the investigation of alternative architectures such as FPGAs to enable higher flexibility for such applications. This paper presents a multi-level overview of power optimization for FPGA-based systems. Several novel design considerations for power reduction are described and discussed as well as the achieved results. The main objective of the presented work is to enable the flexibility of reconfigurable architectures even for low-power applications.