Towards Novel Approaches in Design Automation for FPGA Power Optimization
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
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This paper considers the elaboration of custom pipelines for network packet processing, built upon flexible programmability of pipeline stage granularity. A systematic procedure for accurately characterizing throughput, latency, and FPGA resource requirements, of different programmed pipeline variants is presented. This procedure may be exploited at design time, configuration time, or run time, to program pipeline architectures to meet specific networking application requirements. The procedure is illustrated using three case studies drawn from real-life packet processing at different levels of networking protocol. Detailed results are presented, demonstrating that the procedure estimates pipeline characteristics well, thus allowing rapid architecture space exploration prior to elaboration.