Dynamic power consumption in Virtex™-II FPGA family
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
A Lightweight Approach for Embedded Reconfiguration of FPGAs
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Run-time reconfigurabilility and other future trends
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Proceedings of the conference on Design, automation and test in Europe
A system architecture for reconfigurable trusted platforms
Proceedings of the conference on Design, automation and test in Europe
Dynamic power optimization by exploiting self-reconfiguration in Xilinx Spartan 3-based systems
Microprocessors & Microsystems
Towards Novel Approaches in Design Automation for FPGA Power Optimization
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Energy reduction by systematic run-time reconfigurable hardware deactivation
Transactions on High-Performance Embedded Architectures and Compilers IV
Achieving energy efficiency through runtime partial reconfiguration on reconfigurable systems
ACM Transactions on Embedded Computing Systems (TECS)
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The flexibility of reconfigurable hardware can be exploited to adapt to requirements of applications while run-time. Hardware described functions can be configured dynamically when required, which leads to better usage of chip resources due to reduction of chip area and therefore reduced power consumption. Unfortunately the many restrictions of available run-time reconfigurable hardware architectures has until now limited the integration of such systems in real applications. Also, the high power consumption of reconfigurable architectures makes them suitable for mostly very high performance requiring applications such as signal processing tasks or multimedia applications. In this paper a method for 2D reconfiguration is described, which also enables on-line routing of communication primitives. In order to decrease the power consumption, we also propose a method for adapting signal routing according to power and performance. We demonstrate that there is a trade-off between the power and performance of on-chip signal lines, which can be exploited for on-line adaptation.