Core Communication Interface for FPGAs
Proceedings of the 15th symposium on Integrated circuits and systems design
Networks on Chip: A New Paradigm for Systems on Chip Design
Proceedings of the conference on Design, automation and test in Europe
Power Estimation and Power Measurement of Xilinx Virtex FPGAs: Trade-Offs and Limitations
SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
A Lightweight Approach for Embedded Reconfiguration of FPGAs
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A Timed Petri Net Approach for Pre-Runtime Scheduling in Partial and Dynamic Reconfigurable Systems
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Placement of intermodule connections on partially reconfigurable devices
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Infrastructure for dynamic reconfigurable systems: choices and trade-offs
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Support for partial run-time reconfiguration of platform FPGAs
Journal of Systems Architecture: the EUROMICRO Journal
Conjoining soft-core FPGA processors
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Proceedings of the conference on Design, automation and test in Europe
Real-Time Management of Hardware and Software Tasks for FPGA-based Embedded Systems
IEEE Transactions on Computers
Proceedings of the conference on Design, automation and test in Europe
A Networked, Lightweight and Partially Reconfigurable Platform
ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
A multilayer framework supporting autonomous run-time partial reconfiguration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dynamic power optimization by exploiting self-reconfiguration in Xilinx Spartan 3-based systems
Microprocessors & Microsystems
Ultra-Fast Downloading of Partial Bitstreams through Ethernet
ARCS '09 Proceedings of the 22nd International Conference on Architecture of Computing Systems
Providing memory management abstraction for self-reconfigurable video processing platforms
International Journal of Reconfigurable Computing - Selected papers from ReCoSoc08
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
Bandwidth Management in Application Mapping for Dynamically Reconfigurable Architectures
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Elementary block based 2-dimensional dynamic and partial reconfiguration for Virtex-II FPGAs
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Architecture and operating system support for two-dimensional runtime partial reconfiguration
The Journal of Supercomputing
Run-time generation of partial FPGA configurations
Journal of Systems Architecture: the EUROMICRO Journal
Co-managing software and hardware modules through the juggle middleware
Middleware'11 Proceedings of the 12th ACM/IFIP/USENIX international conference on Middleware
A dynamically reconfigurable communication architecture for multicore embedded systems
Journal of Systems Architecture: the EUROMICRO Journal
Run-time generation of partial FPGA configurations for subword operations
Microprocessors & Microsystems
Co-managing software and hardware modules through the Juggle middleware
Proceedings of the 12th International Middleware Conference
Low-latency histogram equalization for infrared image sequences: a hardware implementation
Journal of Real-Time Image Processing
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Xilinx Virtex FPGAs offer the possibility of dynamic and partial run-time reconfiguration. If a system uses this feature the designer has to take care, that no signal lines cross the border to other reconfigurable regions. Traditional solutions connecting modules on a dynamic and partial reconfigurable system use TBUF elements for connection and separation of the functional blocks. While automalically placing and routing the design, the routing-tool sometimes uses signal lines which cross the module border. The constraints given by the designer are ignored. To solve this problem we use slices instead of TBUF elements which leads to a benefit by using an automatic modular design flow. This paper gives an overview of the used technique and the complete system on a Xilinx XC2V3000 FPGA.