Adaptive histogram equalization and its variations
Computer Vision, Graphics, and Image Processing
Digital Image Processing
Evolutionary Reconfigurable Architecture for Robust Face Recognition
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
Journal of VLSI Signal Processing Systems
Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
A proposed FPGA architecture for mean shift based object tracking with bandwidth constrained sensors
International Journal of Intelligent Systems Technologies and Applications
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This work describes a hardware implementation of the contrast-limited adaptive histogram equalization algorithm (CLAHE). The intended application is the processing of image sequences from high-dynamic-range infrared cameras. The variant of histogram equalization implemented is the one most commonly used today. It involves dividing the image into tiles, computing a transformation function on each of them, and interpolating between them. The contrast-limiting is modified to facilitate the hardware implementation, and it is shown that the error introduced by this modification is negligible. The latency of the design is minimized by performing its successive steps simultaneously on the same frame and by exploiting the vertical blank pause between frames. The resource usage of the histogram equalization module and how it depends on its parameters has been determined by synthesis. The design has been synthesized and tested on a Xilinx FPGA. The implementation supports substituting other dynamic range reduction modules for the histogram equalization component by partial dynamic reconfiguration.