Core Communication Interface for FPGAs
Proceedings of the 15th symposium on Integrated circuits and systems design
Networks on Chip: A New Paradigm for Systems on Chip Design
Proceedings of the conference on Design, automation and test in Europe
Power Estimation and Power Measurement of Xilinx Virtex FPGAs: Trade-Offs and Limitations
SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
A Lightweight Approach for Embedded Reconfiguration of FPGAs
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Prerouted FPGA cores for rapid system construction in a dynamic reconfigurable system
EURASIP Journal on Embedded Systems
A multilayer framework supporting autonomous run-time partial reconfiguration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Secure processing using dynamic partial reconfiguration
Proceedings of the 5th Annual Workshop on Cyber Security and Information Intelligence Research: Cyber Security and Information Intelligence Challenges and Strategies
An interface for a decentralized 2d reconfiguration on xilinx virtex-FPGAs for organic computing
International Journal of Reconfigurable Computing - Selected papers from ReCoSoc08
Decentralized control for dynamically reconfigurable FPGA systems
Microprocessors & Microsystems
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The development of Field Programmable Gate Arrays (FPGAs) had tremendous improvements in the last few years. They were extended from simple logic circuits to complex Systems-on-Chip which enable the integration of complete microcontroller systems and their peripheral devices. Virtex-II FPGAs from Xilinx provide the possibility of dynamic and partial reconfiguration. This can be taken advantage of to substitute inactive parts of a hardware system and adapt the complete chip to a different requirement of an application while run-time. Existing approaches allow reconfiguration of slot based systems while run-time. Unfortunately such systems suffer from the fact, that fixed sized reconfigurable slots are not completely utilized by all functional blocks. Therefore a new 2-dimensional approach is necessary to optimize the placement of functions on the reconfiguration area for the FPGA. Benefit is a reduced chip size which leads to a reduction of power dissipation. This paper describes the method and procedure to include a 2-dimensional placement of reconfigurable blocks and the integration to a run-time system.