SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Run-time reconfigurabilility and other future trends
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Infrastructure for dynamic reconfigurable systems: choices and trade-offs
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Tornado: A self-reconfiguration control system for core-based multiprocessor CSoPCs
Journal of Systems Architecture: the EUROMICRO Journal
Bandwidth Management in Application Mapping for Dynamically Reconfigurable Architectures
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Elementary block based 2-dimensional dynamic and partial reconfiguration for Virtex-II FPGAs
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
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The use of pre-designed and pre-verified hardware modules, also called IP cores, is an important part of the effort to design and implement complex systems. However, many aspects of IP core manipulation are still to be developed. This paper presents an approach to solveproblems related to the dynamic interconnection of hard IP cores. The approach targets system-on-a-chip designs build in a single FPGA device. The paper proposes a communication interface that allows IP cores replacement during the FPGA normal operation. The same interface also allows the communication among distinct IP cores to take place.