Tornado: A self-reconfiguration control system for core-based multiprocessor CSoPCs

Authors:
Armando Astarloa;Aitzol Zuloaga;Unai Bidarte;José Luis Martín;Jesús Lázaro;Jaime Jiménez
Affiliations:
University of the Basque Country, Department of Electronics and Telecommunications, Faculty of Engineering, Urquijo s/n, E-48013 Bilbao, Spain;University of the Basque Country, Department of Electronics and Telecommunications, Faculty of Engineering, Urquijo s/n, E-48013 Bilbao, Spain;University of the Basque Country, Department of Electronics and Telecommunications, Faculty of Engineering, Urquijo s/n, E-48013 Bilbao, Spain;University of the Basque Country, Department of Electronics and Telecommunications, Faculty of Engineering, Urquijo s/n, E-48013 Bilbao, Spain;University of the Basque Country, Department of Electronics and Telecommunications, Faculty of Engineering, Urquijo s/n, E-48013 Bilbao, Spain;University of the Basque Country, Department of Electronics and Telecommunications, Faculty of Engineering, Urquijo s/n, E-48013 Bilbao, Spain
Venue:
Journal of Systems Architecture: the EUROMICRO Journal
Year:
2007

Citing 11
Cited 6

Reconfigurable computing: a survey of systems and software

ACM Computing Surveys (CSUR)
Dynamic hardware plugins in an FPGA with partial run-time reconfiguration

Proceedings of the 39th annual Design Automation Conference
Automating the Design of SOCs Using Cores

IEEE Design & Test
Efficient Metacomputation Using Self-Reconfiguration

FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Partially Reconfigurable Cores for Xilinx Virtex

FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Core Communication Interface for FPGAs

Proceedings of the 15th symposium on Integrated circuits and systems design
A Versatile Framework for FPGA Field Updates: An Application of Partial Self-Reconfiguation

RSP '03 Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP'03)
A Comparison of Five Different Multiprocessor SoC Bus Architectures

DSD '01 Proceedings of the Euromicro Symposium on Digital Systems Design
An Industrial/Academic Configurable System-on-Chip Project (CSoC): Coarse-Grain XXP-/Leon-Based Architecture Integration

DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Support for partial run-time reconfiguration of platform FPGAs

Journal of Systems Architecture: the EUROMICRO Journal
On combining temporal partitioning and sharing of functional units in compilation for reconfigurable architectures

IEEE Transactions on Computers

Modern development methods and tools for embedded reconfigurable systems: A survey

Integration, the VLSI Journal
Multi-level reconfigurable architectures in the switch model

Journal of Systems Architecture: the EUROMICRO Journal
CA-MPSoC: An automated design flow for predictable multi-processor architectures for multiple applications

Journal of Systems Architecture: the EUROMICRO Journal
CoDBT: A multi-source dynamic binary translator using hardware-software collaborative techniques

Journal of Systems Architecture: the EUROMICRO Journal
An autonomous fault tolerant system for CAN communications

IEA/AIE'10 Proceedings of the 23rd international conference on Industrial engineering and other applications of applied intelligent systems - Volume Part III
Function and service pattern analysis for facilitating the reconfiguration of collaboration systems

Computers and Industrial Engineering

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this work we present a self-reconfiguration control focused on multiprocessor core-based systems implemented on FPGA technology. An infrastructure of signals, protocols, interfaces and a controller is exposed to perform safe hardware/software reconfigurations. This infrastructure is part of the Tornado framework that includes other elements such as a multi-context assembler for a reconfigurable processor or a custom design flow developed for the Wishbone IP-Core interconnection specification. We present two applications where the presented control system has been applied, and it is compared with other available approaches.