Communications of the ACM
Improving functional density using run-time circuit reconfiguration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dynamic hardware plugins in an FPGA with partial run-time reconfiguration
Proceedings of the 39th annual Design Automation Conference
JPG - A Partial Bitstream Generation Tool to Support Partial Reconfiguration in Virtex FPGAs
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
Using PARBIT to Implement Partial Run-Time Reconfigurable Systems
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Interconnection Networks Enable Fine-Grain Dynamic Multi-tasking on FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Partially Reconfigurable Cores for Xilinx Virtex
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Dynamic Reconfiguration of Mechatronic Real-Time Systems Based on Configuration State Machines
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Using a Tightly-Coupled Pipeline in Dynamically Reconfigurable Platform FPGAs
DSD '05 Proceedings of the 8th Euromicro Conference on Digital System Design
Tornado: A self-reconfiguration control system for core-based multiprocessor CSoPCs
Journal of Systems Architecture: the EUROMICRO Journal
A multi-mode video-stream processor with cyclically reconfigurable architecture
Proceedings of the 5th conference on Computing frontiers
A Flexible system level design methodology targeting run-time reconfigurable FPGAs
EURASIP Journal on Embedded Systems - Reconfigurable Computing and Hardware/Software Codesign
Schedulability analysis of preemptive and nonpreemptive EDF on partial runtime-reconfigurable FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
Journal of Systems Architecture: the EUROMICRO Journal
Journal of Systems Architecture: the EUROMICRO Journal
Dynamically reconfigurable dataflow architecture for high-performance digital signal processing
Journal of Systems Architecture: the EUROMICRO Journal
An autonomous fault tolerant system for CAN communications
IEA/AIE'10 Proceedings of the 23rd international conference on Industrial engineering and other applications of applied intelligent systems - Volume Part III
A dynamically reconfigurable communication architecture for multicore embedded systems
Journal of Systems Architecture: the EUROMICRO Journal
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Run-time partial reconfiguration of programmable hardware devices can be applied to enhance many applications in high-end embedded systems, particularly those that employ recent platform FPGAs. The effective use of this approach is often hampered by the complexity added to the system development process and by limited tool support. The paper is concerned with several aspects related to the effective exploitation of run-time partial reconfiguration, with particular emphasis on the generation of partial configurations and the run-time utilisation of the reconfigurable resources. The paper presents an approach inspired by the traditional software development: partial configurations are produced by assembling components from a previously created library, thus enabling the embedded application developer to produce the configuration data required for run-time modifications with less effort than is needed with the conventional design flow. A tool that supports this approach is also described. A second set of issues is addressed by a run-time support library that provides facilities for managing the hardware reconfiguration process and the communication with the reconfigured circuits. The use of run-time partial reconfiguration requires a high level of system support. The paper describes one possible approach, presenting a demonstration system developed to support the present work and characterising its performance. In order to clarify the advantages of the approach to run-time reconfiguration discussed in the paper, two small case studies are described, the first on the use of dedicated datapaths for subword operations and the second on two-dimensional pattern-matching for bilevel images. Timing measurements for both cases are included.