A decade of reconfigurable computing: a visionary retrospective
Proceedings of the conference on Design, automation and test in Europe
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Reconfigurable media processing
Parallel Computing - Parallel computing in image and video processing
A Run-Time Reconfigurable Engine for Image Interpolation
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Temporal Partitioning and Scheduling for Reconfigurable Computing
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Decoder-Based Multi-Context Interconnect Architecture
ISVLSI '03 Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
Architecture of a Multi-Context FPGA Using Reconfigurable Context Memory
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Support for partial run-time reconfiguration of platform FPGAs
Journal of Systems Architecture: the EUROMICRO Journal
An efficient list scheduling algorithm for time placement problem
Computers and Electrical Engineering
Implementation of secure applications in self-reconfigurable systems
Microprocessors & Microsystems
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Performance Analysis of Reconfigurations in Adaptive Real-Time Streaming Applications
ACM Transactions on Embedded Computing Systems (TECS)
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This paper presents an approach for development of cost-effective hardware platform for video/image processing. The approach utilizes the SRAM based reconfigurable logic devices (FPGAs) and, their capability of run-time temporal partitioning of logic resources. We propose the architecture for multi-mode video-stream processor with cyclically reconfigurable structure. The proposed architecture has been analyzed on the basis of experiments conducted on AMIRIX AP1000 development system based on Xilinx Virtex-2Pro FPGA. Multi-mode Adaptive Reconfigurable System has been developed, based on Xilinx Virtex-4 FPGA. This platform is capable of supporting the runtime temporal partitioning of on-chip resources. The main component of the research was the introduction of methodology of design for cyclically reconfigurable processor that uses the temporal partitioning mechanism (TPM). TPM allows reuse of the logic and routing resources of an SRAM based FPGA device by the means of partitioning algorithm in to tasks and execution of these tasks in different time slots. This technique allows the reduction of size requirement for FPGA devices, as well as, increase in cost efficiency, and decrease in power consumption of the system compared to systems with statically configured FPGA devices. Applications associated with stereo-vision algorithms and object tracking have been developed and tested on the platform. Finally, the analysis of the cost-effectiveness of this approach has been conducted. This analysis has demonstrated sufficient increase of efficiency in comparison to statically configured FPGA designs. Work also presents optimal conditions at which the use of the architecture would be most cost effective, and where the use of it would be most beneficial. The experimental tests have been done by the means of development of application that are used in the industry in the area of stereo-vision space-born applications.