PipeRench: a co/processor for streaming multimedia acceleration
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
Temporal Partitioning and Scheduling Data Flow Graphs for Reconfigurable Computers
IEEE Transactions on Computers
CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit
Proceedings of the 27th annual international symposium on Computer architecture
Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation
Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation
VIS Speeds New Media Processing
IEEE Micro
ASAP '00 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
SBCCI '00 Proceedings of the 13th symposium on Integrated circuits and systems design
MorphoSys: A Reconfigurable Architecture for Multimedia Applications
SBCCI '98 Proceedings of the 11th Brazilian Symposium on Integrated circuit design
Speeding Up Program Execution Using Reconfigurable Hardware and a Hardware Function Library
VLSID '98 Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing
Reconfigurable Architectures for General-Purpose Computing
Reconfigurable Architectures for General-Purpose Computing
Matrix register file and extended subwords: two techniques for embedded media processors
Proceedings of the 2nd conference on Computing frontiers
Avoiding data conversions in embedded media processors
Proceedings of the 2005 ACM symposium on Applied computing
Avoiding conversion and rearrangement overhead in SIMD architectures
International Journal of Parallel Programming
A multi-mode video-stream processor with cyclically reconfigurable architecture
Proceedings of the 5th conference on Computing frontiers
| Hi-index | 0.00 |
Multimedia processing is becoming increasingly important with wide variety of applications ranging from multimedia cell phones to high definition interactive television. Media processing techniques typically involve the capture, storage, manipulation and transmission of multimedia objects such as text, handwritten data, audio objects, still images, 2D/3D graphics, animation and full-motion video. A number of implementation strategies have been proposed for processing multimedia data. These approaches can be broadly classified into two major categories, namely (i) general purpose processors with programmable media processing capabilities, and (ii) dedicated implementations (ASICs). We have performed a detailed complexity analysis of the recent multimedia standard (MPEG-4) which has shown the potential for reconfigurable computing, that adapts the underlying hardware dynamically in response to changes in the input data or processing environment. We therefore propose a methodology for designing a reconfigurable media processor. This involves hardware-software co-design implemented in the form of a parser, profiler, recurring pattern analyzer, spatial and temporal partitioner. The proposed methodology enables efficient partitioning of resources for complex and time critical multimedia applications.