FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
A multi-mode video-stream processor with cyclically reconfigurable architecture
Proceedings of the 5th conference on Computing frontiers
A Network of Time-Division Multiplexed Wiring for FPGAs
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
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Dynamically-programmable gate arrays (DPGAs) promise lower-cost implementations than conventional FPGAs since they efficiently reuse limited hardware resources in time. One of typical DPGA architectures is a multi-context one. Multi-context FPGAs (MC-FPGAs) have multiple memory bits per configuration bit forming configuration planes for fast switching between contexts. The additional memory planes cause significant overhead in area and power consumption. To overcome the overhead, a fine-grained reconfigurable architecture called reconfigurable context memory (RCM) is presented based on the fact that there are redundancy and regularity in configuration bits between different contexts. Switch blocks are efficiently implemented by using RCM as context decoders and routing switches. By using the RCM in logic blocks, an adaptive multi-context logic block table is introduced where the size of look-up tables and the number of different configuration planes of look-up tables are adaptively determined at each logic block. Moreover, non-volatile ferroelectric-based functional pass-gates are used as components of the RCM to achieve compactness and low static power. Under a constraint of the same number of contexts, an area of the proposed MC-FPGA is 45% of that of the conventional MC-FPGA. In the functional-pass-gate-based evaluation, the area of the proposed MC-FPGA is reduced to 37% of the conventional MC-FPGA one.