Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
The stratixπ routing and logic architecture
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Interconnection Networks Enable Fine-Grain Dynamic Multi-tasking on FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Architecture of a Multi-Context FPGA Using Reconfigurable Context Memory
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
FPGA clock network architecture: flexibility vs. area and power
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
The routability of multiprocessor network topologies in FPGAs
Proceedings of the 2006 international workshop on System-level interconnect prediction
The design and implementation of a low-latency on-chip network
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Virtual Embedded Blocks: A Methodology for Evaluating Embedded Elements in FPGAs
FCCM '06 Proceedings of the 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Packet Switched vs. Time Multiplexed FPGA Overlay Networks
FCCM '06 Proceedings of the 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
On a Pin Versus Block Relationship For Partitions of Logic Graphs
IEEE Transactions on Computers
Predicting the performance of application-specific NoCs implemented on FPGAs
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Improving FPGA performance for carry-save arithmetic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Effect of serialized routing resources on the implementation area of datapath circuits on FPGAS
WSEAS Transactions on Computers
CONNECT: re-examining conventional wisdom for designing nocs in the context of FPGAs
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
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Our investigation into Networks-on-Chip for Field-Programmable Gate Arrays (FPGAs) indicates that fine-grain time-division multiplexing over configurable wires can significantly reduce the number of interconnects needed and therefore reduce chip area. We have investigated the impact of using different proportions of time-multiplexed shared wiring and conventional wiring on the number of wires needed per channel. To do this we have written a scheduler to map benchmarks to the wire sharing architecture. The algorithm developed allows us to trade off between wire count and latency. This is the first time that the statically configured FPGA wiring has been entirely replaced by time-multiplexed wiring. Our results indicate that time-multiplexed wiring could be an effective way of making better use of the on-chip resources and enable the use of on-chip networks with low overheads.