Let's route packets instead of wires
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
Networks on Chip: A New Paradigm for Systems on Chip Design
Proceedings of the conference on Design, automation and test in Europe
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
A modular simulation framework for architectural exploration of on-chip interconnection networks
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
SPIN: A Scalable, Packet Switched, On-Chip Micro-Network
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip
IEEE Transactions on Parallel and Distributed Systems
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
IEEE Transactions on Computers
A Network of Time-Division Multiplexed Wiring for FPGAs
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Leveraging reconfigurability in the hardware/software codesign process
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
A remote memory access infrastructure for global address space programming models in FPGAs
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
| Hi-index | 0.00 |
A fundamental difference between ASICs and FPGAs is that wires in ASICs are designed such that they match the requirements of a particular design. Wire parameters such as length, width, layout and the number of wires can be varied to implement a desired circuit. Conversely, in an FPGA, area is fixed and routing resources exist whether or not they are used, so the goal becomes implementing a circuit within the limits of available resources. The architecture for existing routing structures in FPGAs has evolved over time to suit the requirements of large, localized digital circuits. However, FPGAs now have the capacity to implement networks of such circuits, and system-level interconnection becomes a key element of the design process.Following a standard design flow and using commercial tools, we investigate how this fundamental difference in resource usage affects the mapping of various network topologies to a modern FPGA routing structure. By exploring the routability of different multiprocessor network topologies with 8, 16 and 32 nodes on a single FPGA, we show that the difference between resource utilization of a ring, star, hypercube and mesh topologies is not significant up to 32 nodes. We also show that a fully-connected network can be implemented with at least 16 nodes, but with 32 nodes it exceeds the routing resources available on the FPGA. We also derive a cost metric that helps to estimate the impact of the topology selection based on the number of nodes.