Hardware-software co-design of embedded systems: the POLIS approach
Hardware-software co-design of embedded systems: the POLIS approach
Codesign of embedded systems based on Java and reconfigurable hardware components
DATE '99 Proceedings of the conference on Design, automation and test in Europe
A method to derive application-specific embedded processing cores
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Hardware-software co-design of embedded reconfigurable architectures
Proceedings of the 37th Annual Design Automation Conference
Dhrystone: a synthetic systems programming benchmark
Communications of the ACM
Hardware-Software Cosynthesis for Microcontrollers
IEEE Design & Test
Pentium 4 Performance-Monitoring Features
IEEE Micro
Hardware-software bipartitioning for dynamically reconfigurable systems
Proceedings of the tenth international symposium on Hardware/software codesign
Proceedings of the tenth international symposium on Hardware/software codesign
Dynamic run-time HW/SW scheduling techniques for reconfigurable architectures
Proceedings of the tenth international symposium on Hardware/software codesign
Dynamic hardware/software partitioning: a first approach
Proceedings of the 40th annual Design Automation Conference
System-on-chip beyond the nanometer wall
Proceedings of the 40th annual Design Automation Conference
A Hardware/Software Codesign Method for a General Purpose Reconfigurable Co-Processor
CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
Source Level Debugger for the Sea Cucumber Synthesizing Compiler
FCCM '03 Proceedings of the 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Transaction level modeling: an overview
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Using reconfigurability to achieve real-time profiling for hardware/software codesign
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
An SoC design methodology using FPGAs and embedded microprocessors
Proceedings of the 41st annual Design Automation Conference
Transaction-Level Models for AMBA Bus Architecture Using SystemC 2.0
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
A Portable Programming Interface for Performance Evaluation on Modern Processors
International Journal of High Performance Computing Applications
Profiling soft-core processor applications for hardware/software partitioning
Journal of Systems Architecture: the EUROMICRO Journal
The routability of multiprocessor network topologies in FPGAs
Proceedings of the 2006 international workshop on System-level interconnect prediction
FPGA architecture characterization for system level performance analysis
Proceedings of the conference on Design, automation and test in Europe: Proceedings
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Current technology allows designers to implement complete embedded computing systems on a single FPGA. Using an FPGA as the implementation platform introduces greater flexibility into the design process and allows a new approach to embedded system design. Since there is no cost to reprogramming an FPGA, system performance can be measured on-chip in the runtime environment and the system's architecture can be altered based on an evaluation of the data to meet design requirements. In this article, we discuss a new hardware/software codesign methodology tailored to reconfigurable platforms and a design infrastructure created to incorporate on-chip design tools. This methodology utilizes the FPGA's reconfigurability during the design process to profile and verify system performance, thereby reducing system design time. Our current design infrastructure includes: a system specification tool, two on-chip profiling tools, and an on-chip system verification tool.