System-on-chip beyond the nanometer wall

Authors:
Philippe Magarshack;Pierre G. Paulin
Affiliations:
Central R&D, STMicroelectronics, Crolles cedex, France;Central R&D, STMicroelectronics, Ottawa, ON, Canada
Venue:
Proceedings of the 40th annual Design Automation Conference
Year:
2003

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Abstract

In this paper, we analyze the emerging trends in the design of complex Systems-on-a-Chip for nanometer-scale semiconductor technologies and their impact on design automation requirements, from the perspective of a broad range SoC supplier.We present our vision of some of the key changes that will emerge in the next five years. This vision is characterized by two major paradigm changes. The first is that SoC design will become divided into four mostly non-overlapping distinct abstraction levels. Very different competences and design automation tools will be needed at each level.The second paradigm change is the emergence of domain-specific S/W programmable SoC platforms consisting of large, heterogeneous sets of embedded processors. These will be complemented by embedded reconfigurable hardware and networks-on-chip. A key enabler for the effective us of these flexible SoC platforms, is a high-level parallel programming model supporting automatic specification-to-platform mapping.