Parallel programming models for a multi-processor SoC platform applied to high-speed traffic management

Authors:
Pierre G. Paulin;Chuck Pilkington;Michel Langevin;Essaid Bensoudane;Gabriela Nicolescu
Affiliations:
STMicroelectronics, Ottawa, Canada;STMicroelectronics, Ottawa, Canada;STMicroelectronics, Ottawa, Canada;STMicroelectronics, Ottawa, Canada;Ecole Polytechnique de Montreal, Montreal, Canada
Venue:
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Year:
2004

Citing 10
Cited 12

StepNP: A System-Level Exploration Platform for Network Processors

IEEE Design & Test
A Scalable High-Performance Computing Solution for Networks on Chips

IEEE Micro
A complexity effective communication model for behavioral modeling of signal processing applications

Proceedings of the 40th annual Design Automation Conference
System-on-chip beyond the nanometer wall

Proceedings of the 40th annual Design Automation Conference
Networks on chip

Networks on chip
Hardware support for real-time operating systems

Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Programmers' views of SoCs

Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Application of a Multi-Processor SoC Platform to High-Speed Packet Forwarding

Proceedings of the conference on Design, automation and test in Europe - Volume 3
A comparison of the RTU hardware RTOS with a hardware/software RTOS

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
System-level design: orthogonalization of concerns and platform-based design

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

A multicast inter-task communication protocol for embedded multiprocessor systems

CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
High-level architecture exploration for MPEG4 encoder with custom parameters

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
MPSoC memory optimization using program transformation

ACM Transactions on Design Automation of Electronic Systems (TODAES)
System-level design flow based on a functional reference for HW and SW

Proceedings of the 44th annual Design Automation Conference
Buffer and Register Allocation for Memory Space Optimization

Journal of VLSI Signal Processing Systems
A retargetable parallel-programming framework for MPSoC

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Highly-cited ideas in system codesign and synthesis

CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Developing platform specific model for MPSoC architecture from UML-based embedded software models

Journal of Systems and Software
A platform-based design framework for joint SW/HW multiprocessor systems design

Journal of Systems Architecture: the EUROMICRO Journal
An on-chip interconnect and protocol stack for multiple communication paradigms and programming models

CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
A Safari Through the MPSoC Run-Time Management Jungle

Journal of Signal Processing Systems
Efficient synchronization for embedded on-chip multiprocessors

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper, we describe the MultiFlex multi-processor SoC programming environment, with focus on two programming models: a distributed system object component (DSOC) message passing model, and a symmetrical multi-processing (SMP) model using shared memory. The MultiFlex tools map these models onto the StepNP multi-processor SoC platform, while making use of harware accelerators for message passing and task scheduling. We present the results of mapping an Internet traffic management application, running at 2.5Gb/s.