DAC '97 Proceedings of the 34th annual Design Automation Conference
Hardware-software co-design of embedded systems: the POLIS approach
Hardware-software co-design of embedded systems: the POLIS approach
YAPI: application modeling for signal processing systems
Proceedings of the 37th Annual Design Automation Conference
Hardware/software partitioning of embedded system in OCAPI-xl
Proceedings of the ninth international symposium on Hardware/software codesign
Eclipse: Heterogeneous Multiprocessor Architecture for Flexible Media Processing
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
A Methodology to Design Programmable Embedded Systems - The Y-Chart Approach
Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Design and programming of embedded multiprocessors: an interface-centric approach
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Programming models and HW-SW interfaces abstraction for multi-processor SoC
Proceedings of the 43rd annual Design Automation Conference
Efficient implementation of native software simulation for MPSoC
Proceedings of the conference on Design, automation and test in Europe
A platform-based design framework for joint SW/HW multiprocessor systems design
Journal of Systems Architecture: the EUROMICRO Journal
A high-level virtual platform for early MPSoC software development
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Native MPSoC co-simulation environment for software performance estimation
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
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Heterogeneous MPSoC design where flexible programmable cores are combined with optimized HW co-processors is a quite complex and challenging task. In this paper, we present a system-level design flow that uses a single functional reference for modeling both HW and SW. The models follow an interface-centric design approach based on the TTL interface (Task Transaction Level). TTL models are applied at all three abstraction levels of the design flow: functional, architecture and implementation level. The TTL model at the functional level serves as the functional reference. HW implementations are generated from refined TTL models by behavioral synthesis tooling. Likewise, SW implementations are supported by source code transformations. Both the HW and SW implementations are verified against the functional reference. Details of the complete flow are presented in the paper through an MP3 case study.