Software product lines: practices and patterns
Software product lines: practices and patterns
Component-based design approach for multicore SoCs
Proceedings of the 39th annual Design Automation Conference
Viper: A Multiprocessor SOC for Advanced Set-Top Box and Digital TV Systems
IEEE Design & Test
FORGE: A Framework for Optimization of Distributed Embedded Systems Software
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
System Design Using Kahn Process Networks: The Compaan/Laura Approach
Proceedings of the conference on Design, automation and test in Europe - Volume 1
×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
CASSE: A System-Level Modeling and Design-Space Exploration Tool for Multiprocessor Systems-on-Chip
DSD '04 Proceedings of the Digital System Design, EUROMICRO Systems
Comparing Analytical Modeling with Simulation for Network Processors: A Case Study
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
Modelling, Analysis and Parallel Implementation of an On-line Video Encoder
DFMA '05 Proceedings of the First International Conference on Distributed Frameworks for Multimedia Applications
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
CODES+ISSS '04 Proceedings of the international conference on Hardware/Software Codesign and System Synthesis: 2004
Design and Programming of Embedded Multiprocessors: An Interface-Centric Approach
CODES+ISSS '04 Proceedings of the international conference on Hardware/Software Codesign and System Synthesis: 2004
MPARM: Exploring the Multi-Processor SoC Design Space with SystemC
Journal of VLSI Signal Processing Systems
High-level modeling and simulation of single-chip programmable heterogeneous multiprocessors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ARTS: A System-Level Framework for Modeling MPSoC Components and Analysis of their Causality
MASCOTS '05 Proceedings of the 13th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
Fast and accurate transaction level models using result oriented modeling
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Proceedings of the conference on Design, automation and test in Europe
System-level design flow based on a functional reference for HW and SW
Proceedings of the 44th annual Design Automation Conference
DSD '07 Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools
Software/Hardware Engineering with the Parallel Object-Oriented Specification Language
MEMOCODE '07 Proceedings of the 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign
Compositional constraints generation for concurrent real-time loops with interdependent iterations
IICS'05 Proceedings of the 5th international conference on Innovative Internet Community Systems
JAHUEL: a formal framework for software synthesis
ICFEM'05 Proceedings of the 7th international conference on Formal Methods and Software Engineering
VLSI-DSP based real time solution of DSC-SRI for an ultrasound system
Microprocessors & Microsystems
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We present P-Ware, a framework for joint software and hardware modelling and synthesis of multiprocessor embedded systems. The framework consists of (1) component-based annotated transaction-level models for joint modelling of parallel software and multiprocessor hardware, and (2) exploration-driven methodology for joint software and hardware synthesis. The methodology has the advantage of combining real-time requirements of software with efficient optimization of hardware performance. We describe and apply the methodology to synthesize a scheduler of a H264 video encoder on the Cake multiprocessor. Moreover, experiments show that the framework is scalable while achieving rapid and efficient designs.