A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
A platform-based design framework for joint SW/HW multiprocessor systems design
Journal of Systems Architecture: the EUROMICRO Journal
Cost Analysis for Embedded Systems: Experiments with Priced Timed Automata
Electronic Notes in Theoretical Computer Science (ENTCS)
Proceedings of the Conference on Design, Automation and Test in Europe
A unified design space simulation environment for network-on-chip: fuse-N
International Journal of High Performance Systems Architecture
Multi-granularity noc simulation framework for early phase exploration of SDR hardware platforms
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
PAM-SoC: a toolchain for predicting MPSoC performance
Euro-Par'06 Proceedings of the 12th international conference on Parallel Processing
Microprocessors & Microsystems
| Hi-index | 0.00 |
Designing complex heterogeneous multiprocessor Systemon- Chip (MPSoC) requires support for modeling and analysis of the different layers i.e. application, operating system (OS) and platform architecture. This paper presents an abstract system-level modeling framework, called ARTS, to support the MPSoC designers in modeling the different layers and understanding their causalities. While others have developed tools for static analysis and modeled limited correlations (processor-memory or processor-communication), our model captures the impact of dynamic and unpredictable OS behaviour on processor, memory and communication performance. In particular, we focus on analyzing the impact of application mapping on the processor and memory utilization taking the on-chip communication latency into account. A case-study of a real-time multimedia application consisting of 114 tasks on a 6-processor platform for a hand-held terminal shows our frameworks co-exploration capabilities.