The SpectrumWare approach to wireless signal processing
Wireless Networks
Hardware-software co-design of embedded systems: the POLIS approach
Hardware-software co-design of embedded systems: the POLIS approach
ipChinook: an integrated IP-based design framework for distributed embedded systems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Custom Memory Management Methodology: Exploration of Memory Organisation for Embedded Multimedia System Design
Concurrent execution semantics and sequential simulation algorithms for the metropolis meta-model
Proceedings of the tenth international symposium on Hardware/software codesign
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
ARTS: A System-Level Framework for Modeling MPSoC Components and Analysis of their Causality
MASCOTS '05 Proceedings of the 13th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems
Models of Computation for Networks on Chip
ACSD '06 Proceedings of the Sixth International Conference on Application of Concurrency to System Design
Cross-layer power management in wireless networks and consequences on system-level architecture
Signal Processing - Special section: Advances in signal processing-assisted cross-layer designs
Proceedings of the Conference on Design, Automation and Test in Europe
Microprocessors & Microsystems
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Software-defined radio (SDR) terminals are critical to enable concrete and consecutive inter-working between fourth generation wireless access systems or communication modes. The next generation of SDR terminals is intended to have heavy hardware resource requirements and switching between them will introduce dynamism in respect with timing and size of resource requests. This paper presents a system-level framework which combines a cycle-accurate NoC (Network-on-Chip) simulation environment with a pre-existing SDR simulator, thus enabling a cycle accurate simulation and exploration of such complex, dynamic hardware/software SDR designs. The platform specifications are represented as a virtual architecture by a coarse-grain simulator described in SystemC that includes a set of configuration parameters. The key of our approach is that our simulator environment provides automatic wrapper tools able to explore the SDR platform parameters and simultaneously transmit the interconnection traffic in a cycle-accurate NoC simulator giving the opportunity to examine the impact of different topologies at the system bandwidth at execution time. Our simulation results have shown that we can achieve remarkable improvement at the final performance (65-40%) choosing at the early design phase specific platform configurations.