An Analytical Approach for Dimensioning Mixed Traffic Networks
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Applying Dataflow Analysis to Dimension Buffers for Guaranteed Performance in Networks on Chip
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
CoMPSoC: A template for composable and predictable multi-processor system on chips
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A formal approach to the verification of networks on chip
EURASIP Journal on Embedded Systems
ICATPN'07 Proceedings of the 28th international conference on Applications and theory of Petri nets and other models of concurrency
aelite: a flit-synchronous network on chip with composable and predictable services
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
Design and implementation of an operating system for composable processor sharing
Microprocessors & Microsystems
Multi-granularity noc simulation framework for early phase exploration of SDR hardware platforms
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Microprocessors & Microsystems
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Synchronous Data Flow Graphs (SDFGs) are a useful tool for modeling and analyzing embedded data flow applications, both in a single processor and a multiprocessing context or for application mapping on platforms. Throughput analysis of these SDFGs is ...