A computational logic handbook
A computational logic handbook
Introduction to HOL: a theorem proving environment for higher order logic
Introduction to HOL: a theorem proving environment for higher order logic
IEEE Transactions on Software Engineering - Special issue on formal methods in software practice
Verifying parameterized networks
ACM Transactions on Programming Languages and Systems (TOPLAS)
Systematic Formal Verification for Fault-Tolerant Time-Triggered Algorithms
IEEE Transactions on Software Engineering
Symbolic Model Checking
Computer-Aided Reasoning: An Approach
Computer-Aided Reasoning: An Approach
Computer Networks
Formalizing Inductive Proofs of Network Algorithms
ACSC '95 Proceedings of the 1995 Asian Computing Science Conference on Algorithms, Concurrency and Knowledge
SoCBUS: Switched Network on Chip for Hard Real Time Embedded Systems
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
Interactive Theorem Proving and Program Development
Interactive Theorem Proving and Program Development
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
Using Formal Techniques to Debug the AMBA System-on-Chip Bus Protocol
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
HERMES: an infrastructure for low area overhead packet-switching networks on chip
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
Modeling layered distributed communication systems
Formal Aspects of Computing
Design, Synthesis, and Test of Networks on Chips
IEEE Design & Test
Models of Computation for Networks on Chip
ACSD '06 Proceedings of the Sixth International Conference on Application of Concurrency to System Design
IEEE Transactions on Software Engineering
Formal Verification of CHP Specifications with CADP Illustration on an Asynchronous Network-on-Chip
ASYNC '07 Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems
Transaction-Based Communication-Centric Debug
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Modeling Time-Triggered Protocols and Verifying Their Real-Time Schedules
FMCAD '07 Proceedings of the Formal Methods in Computer Aided Design
A functional formalization of on chip communications
Formal Aspects of Computing
Deadlock prevention in the ÆTHEREAL protocol
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Formal specification of networks-on-chips: deadlock and evacuation
Proceedings of the Conference on Design, Automation and Test in Europe
Easy Formal Specification and Validation of Unbounded Networks-on-Chips Architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A multi-level design methodology of multistage interconnection network for MPSOCs
International Journal of Computer Applications in Technology
Refinement-Based modeling of 3d nocs
FSEN'11 Proceedings of the 4th IPM international conference on Fundamentals of Software Engineering
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The current technology allows the integration on a single die of complex systems-on-chip (SoCs) that are composed of manufactured blocks (IPs), interconnected through specialized networks on chip (NoCs). IPs have usually been validated by diverse techniques (simulation, test, formal verification) and the key problem remains the validation of the communication infrastructure. This paper addresses the formal verification of NoCs by means of a mechanized proof tool, the ACL2 theorem prover. A metamodel for NoCs has been developed and implemented in ACL2. This metamodel satisfies a generic correctness statement. Its verification for a particular NoC instance is reduced to discharging a set of proof obligations for each one of the NoC constituents. The methodology is demonstrated on a realistic and state-of-the-art design, the Spidergon network from STMicroelectronics.