ACTLW - An action-based computation tree logic with unless operator
Information Sciences: an International Journal
Reflections on the Future of Concurrency Theory in General and Process Calculi in Particular
Electronic Notes in Theoretical Computer Science (ENTCS)
Proceedings of the conference on Design, automation and test in Europe
A Model Checking Language for Concurrent Value-Passing Systems
FM '08 Proceedings of the 15th international symposium on Formal Methods
Electronic Notes in Theoretical Computer Science (ENTCS)
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A formal approach to the verification of networks on chip
EURASIP Journal on Embedded Systems
Hi-index | 0.00 |
Few formal verification techniques are currently available for asynchronous designs. In this paper, we describe a new approach for the formal verification of asynchronous architectures described in the high-level language CHP, by using model checking techniques provided by the CADP toolbox. Our proposal is based on an automatic translation from CHP into LOTOS, the process algebra used in CADP. A translator has been implemented, which handles full CHP including the specific probe operator. The CADP toolbox capabilities allow the designer to verify properties such as deadlock-freedom or protocol correctness on substantial systems. Our approach has been successfully applied to formally verify two complex designs. In this paper, we illustrate our technique on an asynchronous Network-on-Chip architecture. Its formal verification highlights the need to carefully design systems exhibiting nondeterministic behavior.