Communicating sequential processes
Communicating sequential processes
Introduction to the ISO specification language LOTOS
Computer Networks and ISDN Systems - Special Issue: Protocol Specification and Testing
A fully abstract model for concurrent constraint programming
TAPSOFT '91 Proceedings of the international joint conference on theory and practice of software development on Colloquium on trees in algebra and programming (CAAP '91): vol 1
An exercise in the automatic verification of asynchronous designs
Formal Methods in System Design
The tangram framework (embedded tutorial): asynchronous circuits for low power
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Communication and Concurrency
Introduction to Process Algebra
Introduction to Process Algebra
Compilation and verification of LOTOS specifications
Proceedings of the IFIP WG6.1 Tenth International Symposium on Protocol Specification, Testing and Verification X
A Graphical Parallel Composition Operator for Process Algebras
FORTE XII / PSTV XIX '99 Proceedings of the IFIP TC6 WG6.1 Joint International Conference on Formal Description Techniques for Distributed Systems and Communication Protocols (FORTE XII) and Protocol Specification, Testing and Verification (PSTV XIX)
SVL: A Scripting Language for Compositional Verification
FORTE '01 Proceedings of the IFIP TC6/WG6.1 - 21st International Conference on Formal Techniques for Networked and Distributed Systems
Compositional Verification Using SVL Scripts
TACAS '02 Proceedings of the 8th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Compiler Construction Using LOTOS NT
CC '02 Proceedings of the 11th International Conference on Compiler Construction
Verifying and Testing Asynchronous Circuits using LOTOS
FORTE/PSTV 2000 Proceedings of the FIP TC6 WG6.1 Joint International Conference on Formal Description Techniques for Distributed Systems and Communication Protocols (FORTE XIII) and Protocol Specification, Testing and Verification (PSTV XX)
Analyzing and verifying locally clocked circuits with the concurrency workbench
GLSVLSI '95 Proceedings of the Fifth Great Lakes Symposium on VLSI (GLSVLSI'95)
Modelling and verification of delay-insensitive circuits using CCS and the concurrency workbench
Information Processing Letters
An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework
ASYNC '05 Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems
Design of On-chip and Off-chip Interfaces for a GALS NoC Architecture
ASYNC '06 Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems
State space reduction for process algebra specifications
Theoretical Computer Science - Algebraic methodology and software technology
On process-algebraic verification of asynchronous circuits
ACSD '06 Proceedings of the Sixth International Conference on Application of Concurrency to System Design
Formal Verification of CHP Specifications with CADP Illustration on an Asynchronous Network-on-Chip
ASYNC '07 Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems
Gate-level modelling and verification of asynchronous circuits using CSPM and FDR
ASYNC '07 Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems
Towards a Unifying CSP approach to Hierarchical Verification of Asynchronous Hardware
Electronic Notes in Theoretical Computer Science (ENTCS)
CADP 2006: a toolbox for the construction and analysis of distributed processes
CAV'07 Proceedings of the 19th international conference on Computer aided verification
BISIMULATOR: a modular tool for on-the-fly equivalence checking
TACAS'05 Proceedings of the 11th international conference on Tools and Algorithms for the Construction and Analysis of Systems
IFM'05 Proceedings of the 5th international conference on Integrated Formal Methods
CADP 2010: a toolbox for the construction and analysis of distributed processes
TACAS'11/ETAPS'11 Proceedings of the 17th international conference on Tools and algorithms for the construction and analysis of systems: part of the joint European conferences on theory and practice of software
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Hardware process calculi, such as Chp (Communicating Hardware Processes), Balsa, or Haste (formerly Tangram), are a natural approach for the description of asynchronous hardware architectures. These calculi are extensions of standard process calculi with particular synchronisation features implemented using handshake protocols. In this article, we first give a structural operational semantics for value-passing Chp. Compared with the existing semantics of Chp defined by translation into Petri nets, our semantics is general enough to handle value-passing Chp with communication channels open to the environment, and is also independent of any particular (2- or 4-phase) handshake protocol used for circuit implementation. We then describe the translation of Chp into the process calculus Lotos (ISO standard 8807), in order to allow asynchronous hardware architectures expressed in Chp to be verified using the Cadp verification toolbox for Lotos. A translator from Chp to Lotos has been implemented and successfully used for the compositional verification of two industrial case studies, namely an asynchronous implementation of the Des (Data Encryption Standard) and an asynchronous interconnect of a NoC (Network on Chip).