Introduction to the ISO specification language LOTOS
Computer Networks and ISDN Systems - Special Issue: Protocol Specification and Testing
A fully abstract model for concurrent constraint programming
TAPSOFT '91 Proceedings of the international joint conference on theory and practice of software development on Colloquium on trees in algebra and programming (CAAP '91): vol 1
Handshake circuits: an asynchronous architecture for VLSI programming
Handshake circuits: an asynchronous architecture for VLSI programming
The tangram framework (embedded tutorial): asynchronous circuits for low power
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Introduction to Process Algebra
Introduction to Process Algebra
Handbook of Process Algebra
Compilation and verification of LOTOS specifications
Proceedings of the IFIP WG6.1 Tenth International Symposium on Protocol Specification, Testing and Verification X
Compositional Verification Using SVL Scripts
TACAS '02 Proceedings of the 8th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Compiler Construction Using LOTOS NT
CC '02 Proceedings of the 11th International Conference on Compiler Construction
An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework
ASYNC '05 Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems
Towards a Unifying CSP approach to Hierarchical Verification of Asynchronous Hardware
Electronic Notes in Theoretical Computer Science (ENTCS)
Proceedings of the conference on Design, automation and test in Europe
Formal specification and analysis of hardware systems in timed Chi
Nordic Journal of Computing
Mathematical modelling of digital hardware systems in timed Chi
MIC '07 Proceedings of the 26th IASTED International Conference on Modelling, Identification, and Control
Translating FSP into LOTOS and networks of automata
IFM'07 Proceedings of the 6th international conference on Integrated formal methods
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A natural approach for the description of asynchronous hardware designs are hardware process algebras, such as Martin's Chp(Communicating Hardware Processes), Tangram, or Balsa, which are extensions of standard process algebras with particular operators exploiting the implementation of synchronisation using handshake protocols. In this paper, we give a structural operational semantics for value-passing Chp. Compared to existing semantics of Chp defined by translation into Petri nets, our semantics handles value-passing Chp with communication channels open to the environment and is independent of any particular (2- or 4-phase) handshake protocol used for circuit implementation. In a second step, we describe the translation of Chp into the standard process algebra Lotos, in order to allow the application of the Cadp verification toolbox to asynchronous hardware designs. A prototype translator from Chp to Lotos has been successfully used for the compositional veri.cation of the control part of an asynchronous circuit implementing the DES (Data Encryption Standard).