Handshake circuits: an asynchronous architecture for VLSI programming
Handshake circuits: an asynchronous architecture for VLSI programming
Communicating sequential processes
Communications of the ACM
The Theory and Practice of Concurrency
The Theory and Practice of Concurrency
An Algebra for Delay-Insensitive Circuits
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
Principles of Asynchronous Circuit Design: A Systems Perspective
Principles of Asynchronous Circuit Design: A Systems Perspective
On Process-algebraic Verification of Asynchronous Circuits
Fundamenta Informaticae - Half a Century of Inspirational Research: Honoring the Scientific Influence of Antoni Mazurkiewicz
Opportunities and Challenges in Process-algebraic Verification of Asynchronous Circuit Designs
Electronic Notes in Theoretical Computer Science (ENTCS)
Translating FSP into LOTOS and networks of automata
IFM'07 Proceedings of the 6th international conference on Integrated formal methods
Model checking the FlexRay physical layer protocol
FMICS'10 Proceedings of the 15th international conference on Formal methods for industrial critical systems
IFM'05 Proceedings of the 5th international conference on Integrated Formal Methods
On Process-algebraic Verification of Asynchronous Circuits
Fundamenta Informaticae - Half a Century of Inspirational Research: Honoring the Scientific Influence of Antoni Mazurkiewicz
| Hi-index | 0.00 |
Formal verification is increasingly important in asynchronous circuit design, since the lack of a global synchronizing clock makes errors due to concurrency (e.g., deadlocks) virtually impossible to detect by means of conventional methods such as simulation. This paper presents a hierarchical approach to asynchronous systems verification using CSP and its model checker FDR. The approach reflects the hierarchical nature of asynchronous hardware synthesis frameworks, for example the Balsa system, and enables the verification of the system at different levels of abstraction against properties such as deadlock, delay insensitivity, conformance and refinement. We demonstrate the feasibility of our approach by automatically detecting errors due to delay sensitivity and deadlock in simple asynchronous hardware components.