Trace theory for automatic hierarchical verification of speed-independent circuits
Trace theory for automatic hierarchical verification of speed-independent circuits
Handshake circuits: an asynchronous architecture for VLSI programming
Handshake circuits: an asynchronous architecture for VLSI programming
Communicating sequential processes
Communications of the ACM
The Theory and Practice of Concurrency
The Theory and Practice of Concurrency
Verifying an infinite family of inductions simultaneously using data independence and FDR
FORTE XII / PSTV XIX '99 Proceedings of the IFIP TC6 WG6.1 Joint International Conference on Formal Description Techniques for Distributed Systems and Communication Protocols (FORTE XII) and Protocol Specification, Testing and Verification (PSTV XIX)
Partial-Order Reduction in Symbolic State Space Exploration
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Verification of Asynchronous Circuits by BDD-based Model Checking of Petri Nets
Proceedings of the 16th International Conference on Application and Theory of Petri Nets
An Algebra for Delay-Insensitive Circuits
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
Trace Theoretic Verification of Asynchronous Circuits Using Unfoldings
Proceedings of the 7th International Conference on Computer Aided Verification
Computer Organization and Design
Computer Organization and Design
Towards a Unifying CSP approach to Hierarchical Verification of Asynchronous Hardware
Electronic Notes in Theoretical Computer Science (ENTCS)
Principles of Asynchronous Circuit Design: A Systems Perspective
Principles of Asynchronous Circuit Design: A Systems Perspective
Reflections on the Future of Concurrency Theory in General and Process Calculi in Particular
Electronic Notes in Theoretical Computer Science (ENTCS)
On Process-algebraic Verification of Asynchronous Circuits
Fundamenta Informaticae - Half a Century of Inspirational Research: Honoring the Scientific Influence of Antoni Mazurkiewicz
On Process-algebraic Verification of Asynchronous Circuits
Fundamenta Informaticae - Half a Century of Inspirational Research: Honoring the Scientific Influence of Antoni Mazurkiewicz
Design and Analysis of a Robust Carbon Nanotube-Based Asynchronous Primitive Circuit
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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This paper reports our experiences of applying process algebras and associated tools (esp. CSP/FDR2) to verify asynchronous circuit designs developed in the Balsa environment. Balsa is an asynchronous logic synthesis system which uses syntax-directed compilation to generate gate-level implementations from high-level descriptions in a parallel programming language (also called Balsa). Previously, we have proposed a unifying approach to compositionally verifying Balsa designs across several abstraction levels. This paper continues our effort by applying and testing our approach on several large-scale real-life case studies. We describe the outcome of verification for the case studies, and also analyse the strengths and limitations of our method.