Asynchronous interface specification, analysis and synthesis
DAC '98 Proceedings of the 35th annual Design Automation Conference
Efficient encoding schemes for symbolic analysis of petri nets
Proceedings of the conference on Design, automation and test in Europe
Conformance and mirroring for timed asychronous circuits
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Symbolic Analysis of Bounded Petri Nets
IEEE Transactions on Computers
Checking Combinational Equivalence of Speed-Independent Circuits
Formal Methods in System Design
Traversal Techniques for Concurrent Systems
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Net Reductions for LTL Model-Checking
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Efficient Reachability Set Generation and Storage Using Decision Diagrams
Proceedings of the 20th International Conference on Application and Theory of Petri Nets
Using Partial Orders For Trace Theoretic Verification Of Asynchronous Circuits
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Timed Trace Theoretic Verification Using Partial Order Reduction
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Combining Simulation and Guided Traversal for the Verification of Concurrent Systems
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Saturation for a General Class of Models
IEEE Transactions on Software Engineering
Exploiting interleaving semantics in symbolic state-space generation
Formal Methods in System Design
Hierarchical Set Decision Diagrams and Automatic Saturation
PETRI NETS '08 Proceedings of the 29th international conference on Applications and Theory of Petri Nets
A New Algorithm for Partitioned Symbolic Reachability Analysis
Electronic Notes in Theoretical Computer Science (ENTCS)
Hazard Checking of Timed Asynchronous Circuits Revisited
Fundamenta Informaticae - Application of Concurrency to System Design, the Sixth Special Issue
Symbolic State-Space Generation of Asynchronous Systems Using Extensible Decision Diagrams
SOFSEM '09 Proceedings of the 35th Conference on Current Trends in Theory and Practice of Computer Science
A Conservative Framework for Safety-Failure Checking
IEICE - Transactions on Information and Systems
Building Efficient Model Checkers using Hierarchical Set Decision Diagrams and Automatic Saturation
Fundamenta Informaticae - Petri Nets 2008
Opportunities and Challenges in Process-algebraic Verification of Asynchronous Circuit Designs
Electronic Notes in Theoretical Computer Science (ENTCS)
Hardware and Petri nets: application to asynchronous circuit design
ICATPN'00 Proceedings of the 21st international conference on Application and theory of petri nets
ICATPN'03 Proceedings of the 24th international conference on Applications and theory of Petri nets
Data representation and efficient solution: a decision diagram approach
SFM'07 Proceedings of the 7th international conference on Formal methods for performance evaluation
Improving static variable orders via invariants
ICATPN'07 Proceedings of the 28th international conference on Applications and theory of Petri nets and other models of concurrency
Verification of software via integration of design and implementation
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
A fine-grained fullness-guided chaining heuristic for symbolic reachability analysis
ATVA'06 Proceedings of the 4th international conference on Automated Technology for Verification and Analysis
Ten years of saturation: a petri net perspective
Transactions on Petri Nets and Other Models of Concurrency V
Structure-based deadlock checking of asynchronous circuits
Journal of Computer Science and Technology - Special issue on Natural Language Processing
Building Efficient Model Checkers using Hierarchical Set Decision Diagrams and Automatic Saturation
Fundamenta Informaticae - Petri Nets 2008
Hazard Checking of Timed Asynchronous Circuits Revisited
Fundamenta Informaticae - Application of Concurrency to System Design, the Sixth Special Issue
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