Trace theory for automatic hierarchical verification of speed-independent circuits
Trace theory for automatic hierarchical verification of speed-independent circuits
Efficient Verification of Parallel Real–Time Systems
Formal Methods in System Design - Special issue on computer aided verification (CAV 93)
Verification of Asynchronous Circuits by BDD-based Model Checking of Petri Nets
Proceedings of the 16th International Conference on Application and Theory of Petri Nets
A Stubborn Attack On State Explosion
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
Automatic Verification of Timed Circuits
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Trace Theoretic Verification of Asynchronous Circuits Using Unfoldings
Proceedings of the 7th International Conference on Computer Aided Verification
Verification of Timed Systems Using POSETs
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Handbook of automated reasoning
Using Partial Orders For Trace Theoretic Verification Of Asynchronous Circuits
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Timed Trace Theoretic Verification Using Partial Order Reduction
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
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Conformance has been used as a correctness criterion for asynchronous circuits. In the case of untimed systems, conformance of an implementation to a specification is equivalent to the failure-freeness between the implementation and the mirror of the specification. For bounded-delay systems, in general this property does not hold. In this paper, we define various notions of failures and examine whether the above property holds or not. We then discuss an alternative and effective algorithm for conformance checking of bounded-delay asynchronous circuits.