Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
A graph-theoretic approach for timing analysis and its implementation
IEEE Transactions on Computers - Special Issue on Real-Time Systems
Modeling and Verification of Time Dependent Systems Using Time Petri Nets
IEEE Transactions on Software Engineering
Symbolic model checking: 1020 states and beyond
Information and Computation - Special issue: Selections from 1990 IEEE symposium on logic in computer science
Checking that finite state concurrent programs satisfy their linear specification
POPL '85 Proceedings of the 12th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
A Stubborn Attack On State Explosion
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
Using Partial Orders to Improve Automatic Verification Methods
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
Conformance and mirroring for timed asychronous circuits
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Verification of Bounded Delay Asynchronous Circuits with Timed Traces
AMAST '98 Proceedings of the 7th International Conference on Algebraic Methodology and Software Technology
Model Checking of Time Petri Nets Based on Partial Order Semantics
CONCUR '99 Proceedings of the 10th International Conference on Concurrency Theory
Partial Order Reduction for Model Checking of Timed Automata
CONCUR '99 Proceedings of the 10th International Conference on Concurrency Theory
Towards Bounded Model Checking for the Universal Fragment of TCTL
FTRTFT '02 Proceedings of the 7th International Symposium on Formal Techniques in Real-Time and Fault-Tolerant Systems: Co-sponsored by IFIP WG 2.2
Abstractions and Partial Order Reductions for Checking Branching Properties of Time Petri Nets
ICATPN '01 Proceedings of the 22nd International Conference on Application and Theory of Petri Nets
Computing a Finite Prefix of a Time Petri Net
ICATPN '02 Proceedings of the 23rd International Conference on Applications and Theory of Petri Nets
Handbook of automated reasoning
Timed Trace Theoretic Verification Using Partial Order Reduction
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
On Stubborn Sets in the Verification of Linear Time Temporal Properties
Formal Methods in System Design
A partial order semantics approach to the clock explosion problem of timed automata
Theoretical Computer Science - Tools and algorithms for the construction and analysis of systems (TACAS 2004)
Relevant Timed Schedules / Clock Valuations for Constructing Time Petri Net Reachability Graphs
FORMATS '08 Proceedings of the 6th international conference on Formal Modeling and Analysis of Timed Systems
Fundamenta Informaticae - Application of Concurrency to System Design, the Sixth Special Issue
Relevant Timed Schedules/Clock Vectors for Constructing Time Petri Net Reachability Graphs
Discrete Event Dynamic Systems
Desynchronization: design for verification
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
On interleaving in timed automata
CONCUR'06 Proceedings of the 17th international conference on Concurrency Theory
Timed unfoldings for networks of timed automata
ATVA'06 Proceedings of the 4th international conference on Automated Technology for Verification and Analysis
Symbolic unfoldings for networks of timed automata
ATVA'06 Proceedings of the 4th international conference on Automated Technology for Verification and Analysis
Fundamenta Informaticae - Application of Concurrency to System Design, the Sixth Special Issue
Reducing Interleaving Semantics Redundancy in Reachability Analysis of Time Petri Nets
ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Modeling and Verification of Discrete Event Systems
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This paper presents an efficient model checking algorithm forone–safe time Petri nets and a timed temporal logic. The approach isbased on the idea of (1) using only differences of timing variablesto be able to construct a finite representation of the set of allreachable states and (2) further reducing the size of thisrepresentation by exploiting the concurrency in the net. Thisreduction of the state space is possible, because the consideredlinear–time temporal logic is stuttering invariant. The firings oftransitions are only partially ordered by causality and a givenformula; therefore the order of firings of independent transitions isirrelevant, and only one of several equivalent interleavings has tobe generated for the evaluation of the given formula. In this paperthe theory of timing verification with time Petri nets and temporallogic is presented, a concrete model checking algorithm is developedand proved to be correct, and some experimental results demonstratingthe efficiency of the method are given.