Introduction to algorithms
Theoretical Computer Science
Symbolic model checking for real-time systems
Information and Computation
An old-fashioned recipe for real time
ACM Transactions on Programming Languages and Systems (TOPLAS)
Efficient Verification of Parallel Real–Time Systems
Formal Methods in System Design - Special issue on computer aided verification (CAV 93)
Partial-Order Methods for the Verification of Concurrent Systems: An Approach to the State-Explosion Problem
The Book of Traces
Model Checking of Real-Time Reachability Properties Using Abstractions
TACAS '98 Proceedings of the 4th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Partial Order Reductions for Timed Systems
CONCUR '98 Proceedings of the 9th International Conference on Concurrency Theory
Timing Assumptions and Verification of Finite-State Concurrent Systems
Proceedings of the International Workshop on Automatic Verification Methods for Finite State Systems
Optikron: A Tool Suite for Enhancing Model-Checking of Real-Time Systems
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
A Stubborn Attack On State Explosion
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
Stubborn sets for reduced state space generation
Proceedings of the 10th International Conference on Applications and Theory of Petri Nets: Advances in Petri Nets 1990
All from One, One for All: on Model Checking Using Representatives
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
Model-Checking for Real-Time Systems
FCT '95 Proceedings of the 10th International Symposium on Fundamentals of Computation Theory
Verification of Timed Systems Using POSETs
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Reducing the number of clock variables of timed automata
RTSS '96 Proceedings of the 17th IEEE Real-Time Systems Symposium
Static guard analysis in timed automata verification
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
Distributed Timed Automata with Independently Evolving Clocks
CONCUR '08 Proceedings of the 19th international conference on Concurrency Theory
Component-Based Design and Analysis of Embedded Systems with UPPAAL PORT
ATVA '08 Proceedings of the 6th International Symposium on Automated Technology for Verification and Analysis
Scenario-based timing verification of multiprocessor embedded applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Partial order reduction for verification of real-time components
FORMATS'07 Proceedings of the 5th international conference on Formal modeling and analysis of timed systems
Journal of Computer Security - Digital Identity Management (DIM 2007)
Layered composition for timed automata
FORMATS'10 Proceedings of the 8th international conference on Formal modeling and analysis of timed systems
Performance evaluation of schedulers in a probabilistic setting
FORMATS'11 Proceedings of the 9th international conference on Formal modeling and analysis of timed systems
Adding invariants to event zone automata
FORMATS'06 Proceedings of the 4th international conference on Formal Modeling and Analysis of Timed Systems
FSTTCS'04 Proceedings of the 24th international conference on Foundations of Software Technology and Theoretical Computer Science
On interleaving in timed automata
CONCUR'06 Proceedings of the 17th international conference on Concurrency Theory
The implementation of mazurkiewicz traces in POEM
ATVA'06 Proceedings of the 4th international conference on Automated Technology for Verification and Analysis
SAT based bounded model checking with partial order semantics for timed automata
TACAS'10 Proceedings of the 16th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Regular set of representatives for time-constrained MSC graphs
Information Processing Letters
A concurrency-preserving translation from time Petri nets to networks of timed automata
Formal Methods in System Design
Symbolically bounding the drift in time-constrained MSC graphs
ICTAC'12 Proceedings of the 9th international conference on Theoretical Aspects of Computing
Avoiding shared clocks in networks of timed automata
CONCUR'12 Proceedings of the 23rd international conference on Concurrency Theory
Lazy abstractions for timed automata
CAV'13 Proceedings of the 25th international conference on Computer Aided Verification
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We present a new approach to the symbolic model checking of timed automata based on a partial order semantics. It relies on event zones that use vectors of event occurrences instead of clock zones that use vectors of clock values grouped in polyhedral clock constraints. We provide a description of the different congruences that arise when we consider an independence relation in a timed framework. We introduce a new abstraction, called catchup equivalence which is defined on event zones and which can be seen as an implementation of one of the (more abstract) previous congruences. This formal language approach helps clarifying what the issues are and which properties abstractions should have. The catchup equivalence yields an algorithm to check emptiness which has the same complexity bound in the worst case as the algorithm to test emptiness in the classical semantics of timed automata. Our approach works for the class of timed automata proposed by Alur-Dill, except for state invariants (an extension including state invariants is discussed informally). First experiments show that the approach is promising and may yield very significant improvements.