Symbolic model checking for real-time systems
Information and Computation
Concurrent control with “readers” and “writers”
Communications of the ACM
Bounded Model Checking for Timed Systems
FORTE '02 Proceedings of the 22nd IFIP WG 6.1 International Conference Houston on Formal Techniques for Networked and Distributed Systems
Partial Order Reductions for Timed Systems
CONCUR '98 Proceedings of the 9th International Conference on Concurrency Theory
Bounded Reachability Checking with Process Semantics
CONCUR '01 Proceedings of the 12th International Conference on Concurrency Theory
Verification of Timed Automata via Satisfiability Checking
FTRTFT '02 Proceedings of the 7th International Symposium on Formal Techniques in Real-Time and Fault-Tolerant Systems: Co-sponsored by IFIP WG 2.2
Partial Order Path Technique for Checking Parallel Timed Automata
FTRTFT '02 Proceedings of the 7th International Symposium on Formal Techniques in Real-Time and Fault-Tolerant Systems: Co-sponsored by IFIP WG 2.2
Towards Bounded Model Checking for the Universal Fragment of TCTL
FTRTFT '02 Proceedings of the 7th International Symposium on Formal Techniques in Real-Time and Fault-Tolerant Systems: Co-sponsored by IFIP WG 2.2
Elements of General Net Theory
Proceedings of the Advanced Course on General Net Theory of Processes and Systems: Net Theory and Applications
IF-2.0: A Validation Environment for Component-Based Real-Time Systems
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
A partial order semantics approach to the clock explosion problem of timed automata
Theoretical Computer Science - Tools and algorithms for the construction and analysis of systems (TACAS 2004)
QEST '06 Proceedings of the 3rd international conference on the Quantitative Evaluation of Systems
SAT-based Reachability Checking for Timed Automata with Diagonal Constraints
Fundamenta Informaticae - Concurrency Specification and Programming (CS&P 2004)
Adding invariants to event zone automata
FORMATS'06 Proceedings of the 4th international conference on Formal Modeling and Analysis of Timed Systems
On interleaving in timed automata
CONCUR'06 Proceedings of the 17th international conference on Concurrency Theory
Layered composition for timed automata
FORMATS'10 Proceedings of the 8th international conference on Formal modeling and analysis of timed systems
Exploiting step semantics for efficient bounded model checking of asynchronous systems
Science of Computer Programming
Symbolic model checking for temporal-epistemic logic
Logic Programs, Norms and Action
Beyond lassos: complete SMT-Based bounded model checking for timed automata
FMOODS'12/FORTE'12 Proceedings of the 14th joint IFIP WG 6.1 international conference and Proceedings of the 32nd IFIP WG 6.1 international conference on Formal Techniques for Distributed Systems
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We study the model checking problem of timed automata based on SAT solving. Our work investigates alternative possibilities for coding the SAT reductions that are based on parallel executions of independent transitions. While such an optimization has been studied for discrete systems, its transposition to timed automata poses the question of what it means for timed transitions to be executed “in parallel”. The most obvious interpretation is that the transitions in parallel take place at the same time (synchronously). However, it is possible to relax this condition. On the whole, we define and analyse three different semantics of timed sequences with parallel transitions. We prove the correctness of the proposed semantics and report experimental results with a prototype implementation.